An IFC NAND problem on the ls1021a board

[hwei]

Hi,

I meet a NAND read/write problem under u-boot.

My board is booting from NAND but after that I fail to read/write the NAND flash.

While I issue "nand bad", all blocks are displayed.

The result of "nand info" is right:

Device 0: nand0, sector size 512 KiB

  Page size      4096 b

  OOB size        224 b

  Erase size   524288 b

Could anyone show me any ideas?

Thanks

[yipingwang]

Hello H Wei,

Do you use LS1021QDS Rev A? If so please configure SW9[3]=1, because NAND power should be 3.3 V.

SW9[3]  0  BVDD Voltage Select:
0 : Preset BVDD to 1.8V
1 : Preset BVDD to 3.3V

Have a great day,
Yiping

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[hwei]

Hi Yiping,

Thanks for your reply,

It's not the QDS board but a custom board.

There are two NAND flashes on my board and they locate at CS0 and CS2, but I can only enable the CS0.

If I try to enable CS2, this error will occur and I can use neither of them.

I set the CONFIG_SYS_CSPR2 to CONFIG_SYS_CSPR0 + 0x10000 and expand CONFIG_SYS_NAND_BASE_LIST and

CONFIG_SYS_MAX_NAND_DEVICE in u-boot, but just CS0 can be found in u-boot.

Is there any more modification I need to make to enable both of them?

[yipingwang]

Hello H Wei,

Do you change the configuration similar as the following.

#define CONFIG_SYS_NAND2_CSPR                                                                                            (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) + 0x10000 \

                                                        | CSPR_PORT_SIZE_8      \

                                                        | CSPR_MSEL_NAND        \

                                                        | CSPR_V)

#define CONFIG_SYS_CSPR2_EXT	CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2	CONFIG_SYS_NAND2_CSPR
#define CONFIG_SYS_AMASK2	CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2	CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0	CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1	CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2	CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3	CONFIG_SYS_NAND_FTIM3

Have a great day,
Yiping

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[hwei]

Hi Yiping,

Yes, I did the exactly same thing, it didn't work.

I have tried to update CONFIG_SYS_NAND_BASE_LIST and CONFIG_SYS_MAX_NAND_DEVICE too, still just the CS0 can be found.

Do you have any ideas about it?

I cannot enable the two NAND flashes in Kernel too, it prompts:

fsl_ifc_nand_probe: address did not match any chip selects

Can it be a chip select error?

Thanks

[yipingwang]

Hello H Wei,

You could check whether IFC_CS2 is asserted when access NAND2 address.

Would you please send your modified header file to me to do more verification?

Have a great day,
Yiping

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[hwei]

Hi Yiping,

Sorry, I didn't find out how to attach a file.

But here is the NAND part in my header file:

/* NAND Flash on IFC */

#define CONFIG_NAND_FSL_IFC

#define CONFIG_SYS_NAND_BASE        0x7e800000

#ifdef CONFIG_PHYS_64BIT

#define CONFIG_SYS_NAND_BASE_PHYS    0xf7e800000ull

#else

#define CONFIG_SYS_NAND_BASE_PHYS    CONFIG_SYS_NAND_BASE

#endif

#ifdef CONFIG_PHYS_64BIT

#define CONFIG_SYS_NAND_CSPR_EXT    (0x0f)

#else

#define CONFIG_SYS_NAND_CSPR_EXT    (0x0)

#endif

#define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \

                | CSPR_PORT_SIZE_8    \

                | CSPR_MSEL_NAND    \

                | CSPR_V)

#define CONFIG_SYS_NAND2_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) + 0x10000\

                | CSPR_PORT_SIZE_8    \

                | CSPR_MSEL_NAND    \

                | CSPR_V)

#define CONFIG_SYS_NAND_AMASK    IFC_AMASK(64*1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN  \

                | CSOR_NAND_ECC_DEC_EN   \

                | CSOR_NAND_ECC_MODE_4   \

                | CSOR_NAND_RAL_3    \

                | CSOR_NAND_PGS_4K   \

                | CSOR_NAND_SPRZ_224    \

                | CSOR_NAND_PB(128)) 

#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_SYS_NAND_FTIM0        (FTIM0_NAND_TCCST(0x7) | \

                    FTIM0_NAND_TWP(0x18)   | \

                    FTIM0_NAND_TWCHT(0x7) | \

                    FTIM0_NAND_TWH(0xa))

#define CONFIG_SYS_NAND_FTIM1        (FTIM1_NAND_TADLE(0x32) | \

                    FTIM1_NAND_TWBE(0x39)  | \

                    FTIM1_NAND_TRR(0xe)   | \

                    FTIM1_NAND_TRP(0x18))

#define CONFIG_SYS_NAND_FTIM2        (FTIM2_NAND_TRAD(0xf) | \

                    FTIM2_NAND_TREH(0xa) | \

                    FTIM2_NAND_TWHRE(0x1e))

#define CONFIG_SYS_NAND_FTIM3           0x0

#define CONFIG_SYS_NAND_BASE_LIST    {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE + 0x10000}

#define CONFIG_SYS_MAX_NAND_DEVICE    2

#define CONFIG_MTD_NAND_VERIFY_WRITE

#define CONFIG_CMD_NAND

#define CONFIG_SYS_NAND_BLOCK_SIZE    (512 * 1024)

#define CONFIG_SYS_CSPR0_EXT        CONFIG_SYS_NAND_CSPR_EXT

#define CONFIG_SYS_CSPR0        CONFIG_SYS_NAND_CSPR

#define CONFIG_SYS_AMASK0        CONFIG_SYS_NAND_AMASK

#define CONFIG_SYS_CSOR0        CONFIG_SYS_NAND_CSOR

#define CONFIG_SYS_CS0_FTIM0        CONFIG_SYS_NAND_FTIM0

#define CONFIG_SYS_CS0_FTIM1        CONFIG_SYS_NAND_FTIM1

#define CONFIG_SYS_CS0_FTIM2        CONFIG_SYS_NAND_FTIM2

#define CONFIG_SYS_CS0_FTIM3        CONFIG_SYS_NAND_FTIM3

#define CONFIG_SYS_CSPR2_EXT        CONFIG_SYS_NAND_CSPR_EXT

#define CONFIG_SYS_CSPR2        CONFIG_SYS_NAND2_CSPR

#define CONFIG_SYS_AMASK2        CONFIG_SYS_NAND_AMASK

#define CONFIG_SYS_CSOR2        CONFIG_SYS_NAND_CSOR

#define CONFIG_SYS_CS2_FTIM0        CONFIG_SYS_NAND_FTIM0

#define CONFIG_SYS_CS2_FTIM1        CONFIG_SYS_NAND_FTIM1

#define CONFIG_SYS_CS2_FTIM2        CONFIG_SYS_NAND_FTIM2

#define CONFIG_SYS_CS2_FTIM3        CONFIG_SYS_NAND_FTIM3

Thanks

[yipingwang]

Hello H Wei,

I didn't find problem in the u-boot configuration file.

Probably there is hardware problem on your target, have you tried whether it would be different if only enabling CS2 NAND and with CS0 NAND disabled.

Have a great day,
Yiping

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[hwei]

Hi Yiping,

I have made both two NANDs work in linux, but there is still some problem if I enable the CS2 NAND in u-boot, so I disable it temporarily and leave it behind.

Thanks