I am having a similar problem to RC Reddy.
My current procedure is:
run debug_halt_off (in uboot)
/rf-util/rftool -i rf2 –r AD9361R2_TX1A_TX2A_RX1A_RX2A_LB_751_782_MHz_LTE_10_MHz_AGC_Split_Gain_Table_ver1.0.8.txt --synth_table SynthLUT_40_FDD_v2.txt
/rf-util/rftool -i rf2 -c init_lte_10mhz --band 7 -m 2T2R --dl_delay 0x0001 --ul_delay 0x8070
/rf-util/rftool -i rf2 -c init_pps --pps_source nlm_pps
/rf-util/rftool -i rf2 -c time_sync_start
/rf-util/rftool -i rf2 –S
/ipc/dsp_bt aic_loopback_9x31_rel.bin
which leads to getting a message:
root@bsc913x:~# /rf-util/rftool -i rf2 -S
fsl-aic ff650000.aic: rf2:sync cleared 80000000
root@bsc913x:~# /ipc/dsp_bt aic_loopback_9x31_rel.bin
===DSP boot Application===(1.1.02)==
SYSTEM MAP
DSP PrivArea: Addr=38000000 Size=8000000
Shared CtrlArea: Addr=37000000 Size=1000000
DSP Core0 M2: Addr=b0000000 Size=80000
DSP Core1 M2: Addr=0 Size=0
DSP M3: Addr=0 Size=0
PA CCSRBAR: Addr =ff700000 Size=100000
DSP CCSRBAR: Addr =ff600000 Size=100000
PA Shared Area: Addr=10000000 Size=f000000
DSP Shared Area: Addr=1f000000 Size=1000000
DSP READY SET
Copy Part b0000000 120c6
Copy Part b0014000 2f0c
Copy Part ff618108 4
DSP image copied
sleep 4 sec
DSP HW Sem1 value not correctly set, value=0
DSP Boot Failed, Please reset