# E6500 Watchdog Interval

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## E6500 Watchdog Interval

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Contributor III

Hello I was wondering how to set the interval for the watchdog time on the E6500? I am doing this as a bareboard project and have set the MSR[CE] bit to 1 and also the TSR[WP] bit to 1 as well. Now I would like to specify the interval and also be able to reset watchdog timer as well. Any help is appreciate. Thanks!

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• ### Qonverge

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2,585 Views
NXP Employee

Please refer to the AN2804: Watchdog Timer for e500:

and associated software example:

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2,586 Views
NXP Employee

Please refer to the AN2804: Watchdog Timer for e500:

and associated software example:

2,585 Views
Contributor III

Hello ufedor‌,

I have a question regarding the timers used for the watchdog. My T2080 system clock is 100Mhz. Now it states in the manual my platform clock is the ratio of the bits in RCW configuration. My configuration is 6:1 so my Platform clock is 600Mhz. For the time base register the clock is Platfrom clock / 16. The time base register also has a divisor which is set to 16. My time base clock then is 600Mhz/256. Now the equation I am using to calculate the bit to watch for the watchdog timer is:

period = 64 - (ln(time*600Mhz/256)/ln(2))

So in order to wait approximately one second I set the period to be 21. However when I use a printf() to show when my interrupt occurs it is way faster than 1 second. I was wondering if I am calculating my clock frequency wrong or something else is wrong. Also, if there is a way to create a loop that is approximately 1 second delay that might be better to verify my timing but I am not sure how to calculate it. Thanks for your help!

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NXP Employee

You wrote:

> The time base register also has a divisor which is set to 16.

Sorry, where this is stated?

2,585 Views
Contributor III

Thanks for the help! However I can't seem to find where the Core Complex Bus cycles are defined for the E6500? Or is the watchdog timer for it different?

2,585 Views
NXP Employee

In the e6500 the Time Base is clocked by the SoC (TBCLK).