VREF and Multiple ADCs on Kinetis

[Jeinstei]

I noticed that if I have two ADC modules in a PE project, then it complains that the VREF pins can't be used by both modules at the same time. It gives a "peripheral is in use"  message. Is this a PE bug?

[ProcessorExpert]

Hello,

this is not a bug, see the link below for details:

https://community.freescale.com/message/94772#94772

best regards
Vojtech Filip
Processor Expert Support Team

[Jeinstei]

This doesn't seem to make any sense as it is representing the ADC modules in the processors as devices that conflict, when they do not. There's currently nothing in the help file that describes this nor is this restriction inherent in the processor itself.

I thought that pin sharing required some fancy footwork; I currently have it setup on both modules, and it sys "peripheral must be set and initialized in another module" when it IS initialized and set up in another module.

It seems curious that such bus signals should have peripheral restrictions levied on them.

[ProcessorExpert · Accepted solution]

Hello,

the pin sharing button must be un-pressed in one ADC_LDD. As far as I know, this is documented in the PEx help and some comments are also in PEx cheatsheets.

 Help -> Help Contenst

 Help -> Cheat Sheets...

However, I am passing your complain to developers, to consider improving this behavior.

best regards
Vojtech Filip
Processor Expert Support Team