T4241 PCIe and SGMII Issue

[Venkat_Vellanki]

Hi NXP ,

We are using T4241 Processor , K7 FPGA is connected to PCIe4 via Serdes4 (x2gen2).

Similarly in the same Serdes4 PCIe switch was connected (x4gen2).

Similarly in  Serdes3 ,8 SGMII's are connected .

Problem :

• Every time upon power on PCIe switch is getting enumerated properly with x4gen2, K7 FPGA is not getting enumerated .
• Even though PHY is getting detected in u-boot using mii commands , unable to ping them .

Observations:

• We have issued reset to the PCIe4 controller and same has been observed .
• Every time PCIe switch is getting enumerated with x4gen2 upon power on immediately
• Verified K7,Serdes4 voltages and were proper.
• Replaced the data lines between K7 and Processor
• Checked the LTSSM status of RC and it was in 0xC(POLL_COMPLIANCE) - Unable to receive packets from EP .
• Checked the LTSSM status of EP and it was failing at Configuration and L0 path .
• After 40 seconds upon power on and after giving reset to proesser in u-boot , K7 is getting enumerated properly with x2gen2.
• Issued reset only to PEX4 and same has been observed .
• We were able to configure only 1 SGMII  out of 8, PHY is getting detected at u-boot and FMAN is proper.
• Checked Serdes3 reference clock and able to get 100MHz proper frequency .

Queries:

• Is processor delaying PCIe PERST , if in that case PCIe switch is always getting enumerated properly(PCIe switch has PERST connected externally)?
• Any register to know weather PERST of PCIe4 is in asserted or de-asserted ?
• Can we suspect both SGMII and PCIe EP are improper due to any issue in Serdes  ?

Please help us in resolving this issue.

Thanks,

Venkat Vellanki.

[yipingwang]

Lets take PCie issue first. It seems like the FPGA configuration does not complete in time for the link to train to L0. I have pasted my questions inline, please check and respond.

You may try with link width limited to x1 with FPGA.

We are using T4241 Processor , K7 FPGA is connected to PCIe4 via Serdes4 (x2gen2).

Similarly in the same Serdes4 PCIe switch was connected (x4gen2).

NXP: Can you show me in the form of block diagram as to how PCIe switch and K7 are conencted? It seems that K7 is connected to PCIe4 (x2) and switch to PCIe3 (x4)

Similarly in  Serdes3 ,8 SGMII's are connected .

Problem :

Every time upon power on PCIe switch is getting enumerated properly with x4gen2, K7 FPGA is not getting enumerated .

Even though PHY is getting detected in u-boot using mii commands , unable to ping them .

NXP: Which PHY is being reffered to? Could you add the PHY's also to block diagram?

Observations:

We have issued reset to the PCIe4 controller and same has been observed .

NXP: How have you issued reset? Please share procedure.

Every time PCIe switch is getting enumerated with x4gen2 upon power on immediately Verified K7,Serdes4 voltages and were proper.

Replaced the data lines between K7 and Processor

NXP: What does this mean?

Checked the LTSSM status of RC and it was in 0xC(POLL_COMPLIANCE) - Unable to receive packets from EP .

Checked the LTSSM status of EP and it was failing at Configuration and L0 path .

NXP: It seems to be stuck in configuration stage. Can you try to configure the FPGA with x1 and try?

After 40 seconds upon power on and after giving reset to proesser in u-boot , K7 is getting enumerated properly with x2gen2.

Issued reset only to PEX4 and same has been observed .

NXP: Same means what?

We were able to configure only 1 SGMII  out of 8, PHY is getting detected at u-boot and FMAN is proper.

Checked Serdes3 reference clock and able to get 100MHz proper frequency .

Queries:

Is processor delaying PCIe PERST , if in that case PCIe switch is always getting enumerated properly(PCIe switch has PERST connected externally)?

NXP: PERST is not a processor signal. Where have you conencted PERST on your board?

Any register to know weather PERST of PCIe4 is in asserted or de-asserted ?

NXP: PERST is not a SoC signal

Can we suspect both SGMII and PCIe EP are improper due to any issue in Serdes  ?

NXP: Lets take one issue at a time.

[Venkat_Vellanki]

Hi yipingwang,

Thanks for the response.

Both the issues were solved and it's just a reset issue.

Thanks,

Venkat Rao Vellanki.