Problem using PEx Ethernet_LDD Driver

[kenansun]

Hi!

I'm trying to use the Ethernet_LDD driver generated by PEx (v10.4) to control an external Ethernet PHY chip. I also use the code in "Tpyical Usage" of the "Helps on Component". To configure the PHY, I need to write the Control Register, as well as to read the Status Register.

Now, it seems there is no problems with reading or writing a Control Register:

• I send a value and then I can read the same value;
• I send a reset command, and I read the default value.

But the problem is that

• the Status Register seems always stay at its default value, no matter what I write to the Control Register.
• I tried to seed or receive an Ethernet Frame using the "SendFrame" or "ReceiveFrame" function, but it seems not work neither.
• There's no interrupt coming when I tried to send a frame.

Note that I'm working on the TWR-K60F120M Tower system board and I'm using the TWR-SER module. I'm not intended to use the MQX this time.

My questions are:

• Is there anyone who has ever used this PEx Ethernet Driver, specially the demo code in the "Helps on Component"?
• What is the most possible reason for a failure of changing the status register?

Thanks!

[LadislavVadkerti]

Hi,

the Typical Usage example is based on a working application. Which bit of the external PHY chip's status register do you expect to change? I think that only the auto-negotiation bit is affected by a write to the control register and the auto-negotiation process must be successfully completed (the connected network device must support it). The external PHY chip must be configured properly to send/receive frames, otherwise the data remains in the ENET module's FIFO.

Best regards,

Ladislav Vadkerti

Freescale Processor Expert Team

[kenansun]

Thanks for your helpful answer!

1. Which bit I expect to change?

     In fact, I wanted to configure the PHY to Loop-back enalbed, 100Mbps, Duplex Mode and without Auto-negotiation, so I write the command into its Control Register. After verifying the value in the Control Register is correct, I then go to read the Status Register. But the only bit that changed is the "Link Status". The other bits are all at their default values. Note that by default, the 4 bits 100B/10B Full Duplex, 100B/10B Half Duplex are all showed 1 and the Auto-Negotiation Ability bit is also 1.

2. The PHY must be configured properly to send/received frames.

     I don't quite understand "be configured properly". BUT it does seem that all data remains in the ENET queue. I think the main reason is that the interrupt routine is never called, so neither the frame can be removed from the transmit queue nor it can be added into the receive queue. I tried to look for where in the generated codes the interrupt is enabled, but unfortunately I did't find that. Even when I enabled the Rx/Tx interrupt manually, still nothing changed :smileysad:

3. About the demo codes in Help

I'm using the demo codes in the Component help, and I looked through it and it seems to me that everything is OK. But I'm still wondering if these codes are reliable?

Thanks very much!

[LadislavVadkerti]

Hi,

1. Capability bits (10/100Mbps half/full duplex) have permanent values reflecting the abilities of the PHY chip. These don't change.

2. You must select MII or RMII according to your component settings. If you have RMII, the RMII reference clock should be from the same clock source for the K60 as for the PHY chip. In the RMII mode the TX clock is coming from the PHY chip. Try a slower speed first (10Mbps).

The interrupt routine is called after a frame is transmitted, not before. If the transmit data is hanging in the FIFO, you will not receive an interrupt.

3. As I wrote, the examples are based on a functional project's code.

Best regards,

Ladislav Vadkerti

Freescale Processor Expert Team