How important is it that the PE FIFO size for K60 SPI peripherals is wrong?

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How important is it that the PE FIFO size for K60 SPI peripherals is wrong?

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Symbolic
Contributor III

I am running CW 10.5 Build 130916

I have generated SPI code for the K60DN512VMD10 chip (for SPI2)

In the attribute set list section, it will only accept 1 and 16 for both the HW input buffer size and the HW output buffer size.

This is incorrect (AFAICT), the values should be 1 or 4.

However, I am not sure this affects any of the generated code at all.

How important is this error?

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vfilip
NXP Employee
NXP Employee

Hello,

I must confirm that this is really bug in latest version of PEx. However I think it should not influence code functionality. You can for example compare generated code when you set buffer size to 1 and to 16, the only difference is in DIS_TXF/DIS_RXF bitfields in MCR register. DIS_TXF/DIS_RXF bit-fields disable/enable FIFO -> size 4 or 16 should not influence driver functionality.

We will fix it for next release of PEx.

We are sorry for inconvenience.

Best regards

Vojtech Filip

Processor Expert Support Team

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vfilip
NXP Employee
NXP Employee

Hello,

I must confirm that this is really bug in latest version of PEx. However I think it should not influence code functionality. You can for example compare generated code when you set buffer size to 1 and to 16, the only difference is in DIS_TXF/DIS_RXF bitfields in MCR register. DIS_TXF/DIS_RXF bit-fields disable/enable FIFO -> size 4 or 16 should not influence driver functionality.

We will fix it for next release of PEx.

We are sorry for inconvenience.

Best regards

Vojtech Filip

Processor Expert Support Team

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