My target is K20D72M Tower Board and I am using Code Warrior 10.4. Processor Expert PDB Peripheral Initialization component provides three Pulse-outs (0 thru 2). How can these be assigned to physical signals with individual rising/falling edge delays?
Thanks,
-Irwin
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Hi,
I don't think that this is possible. These are just internal signals, according to the reference manual : "Individual PDB pulse-out signals control each CMP Sample/Window timing".
I suggest using TimerUnit_LDD or Init_FTM component for generation of timed signal.
best regards
Petr Hradsky
Processor Expert Support Team
Hi,
I don't think that this is possible. These are just internal signals, according to the reference manual : "Individual PDB pulse-out signals control each CMP Sample/Window timing".
I suggest using TimerUnit_LDD or Init_FTM component for generation of timed signal.
best regards
Petr Hradsky
Processor Expert Support Team