Capturing frames from an Aptina MT9V024 by an iMX51 custom board.

[antoniotringali]

 Hi,

I am trying to port a new kernel (4.18.6) to an old iMX51 custom board. I am reading (maybe outdated) documentation and then some new one. 

 I understand that a CMOS sensor chip attached to the iMX CSI parallel port can be controlled by the Aptina driver. When the  board is booted I see the creation of /dev/video0 through /dev/video4 and the mt9v032 subdevice (it is correctly detected as I2C-attached at address 0x48), but no /dev/media0. Tracing on V4L modules I see that __video_register_device() function should be executed in such a case. I am also using imx-media from drivers/staging/media/imx.  An application such as fswebcam fails to snap a frame.

 I have seen configurations like the one below for iMX6, but not for older boards such as mine. I am starting to think that, barring DTS mistakes on my side, the imx-media modules in driver/staging/media/imx do not support iMX51. 

 For reference this is what I put in the DTS:

&i2c1 {
    clock_frequency = <100000>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_i2c1>;
    status = "okay";

    // Documentation/devicetree/bindings/media/video-interfaces.txt
    camera: mt9v024m@48 {
        compatible = "aptina,mt9v024m";
        reg = <0x48>;

        vddio-supply   = <&reg3v3>;
        vddcore-supply = <&reg3v3>;

        clock-frequency = <26000000>;
        clocks = <&mclk 0>;
        clock-names = "cmos_sysclk";

        port {
            mt9v024m_out: endpoint {
                link-frequencies = /bits/ 64
                    <13000000 26600000 27000000>;
                remote-endpoint = <&ipu_csi1_camera>;

                bus-width = <10>;
                hsync-active = <1>;
                vsync-active = <1>;
                data-active = <1>;
                pclk-sample = <1>;
            };
        };
    };
};

&ipu_csi0 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_ipu1_csi0>;
};

&ipu_csi1_camera {
    remote-endpoint = <&mt9v024m_out>;
    bus-width = <10>;
    hsync-active = <1>;
    vsync-active = <1>;
    data-active = <1>;
    pclk-sample = <1>;
};

 These are the lines dedicated to the CMOS sensor chip:

        pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */
            fsl,pins = <
                MX51_PAD_CSI1_D8__CSI1_D8               0x80000000
                MX51_PAD_CSI1_D9__CSI1_D9               0x80000000
                MX51_PAD_CSI1_D10__CSI1_D10             0x80000000
                MX51_PAD_CSI1_D11__CSI1_D11             0x80000000
                MX51_PAD_CSI1_D12__CSI1_D12             0x80000000
                MX51_PAD_CSI1_D13__CSI1_D13             0x80000000
                MX51_PAD_CSI1_D14__CSI1_D14             0x80000000
                MX51_PAD_CSI1_D15__CSI1_D15             0x80000000
                MX51_PAD_CSI1_D16__CSI1_D16             0x80000000
                MX51_PAD_CSI1_D17__CSI1_D17             0x80000000
                MX51_PAD_CSI1_D18__CSI1_D18             0x80000000
                MX51_PAD_CSI1_D19__CSI1_D19             0x80000000
                MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       0x80000000
                MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         0x80000000
                MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         0x80000000
            >;
        };


 And this is the DTSI defining the video endpoints:

        ipu: ipu@40000000 {
            #address-cells = <1>;
            #size-cells = <0>;
            compatible = "fsl,imx51-ipu";
            reg = <0x40000000 0x20000000>;
            interrupts = <11 10>;
            clocks = <&clks IMX5_CLK_IPU_GATE>,
                 <&clks IMX5_CLK_IPU_DI0_GATE>,
                 <&clks IMX5_CLK_IPU_DI1_GATE>;
            clock-names = "bus", "di0", "di1";
            resets = <&src 2>;

            ipu_csi0: port@0 {
                reg = <0>;

                ipu_csi1_camera: endpoint {
                };
            };

            ipu_csi1: port@1 {
                reg = <1>;

                ipu_csi2_camera: endpoint {
                };
            };

            ipu_di0: port@2 {
                reg = <2>;

                ipu_di0_disp1: endpoint {
                };
            };

            ipu_di1: port@3 {
                reg = <3>;

                ipu_di1_disp2: endpoint {
                };
            };

            vpu: vpu@83ff4000 {
                compatible = "fsl,imx51-vpu";
                reg = <0x83ff4000 0x1000>;
                interrupts = <9>;
                clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
                         <&clks IMX5_CLK_VPU_GATE>;
                clock-names = "per", "ahb";
                resets = <&src 1>;
                iram = <&iram>;
            };
        };


 And outside of the previous segment in the DTSI:

    capture-subsystem {
        compatible = "fsl,imx-capture-subsystem";
        ports = <&ipu_csi0>;
    };

 I thank you in advance for any kind answer helping me to understand...

 Have a nice day,
Antonio Tringali