Bug Report CW11.1 56F8322 PWMC1

[jjt]

PWMC1_SetRatio15 calculates the set edge value using SM0 for ALL channels (including SM1, SM2 channels). Should be using SM1_INIT and _VAL1 for channels 2,3 and SM2_INIT, _VAL1 for channels 4,5.

register word SetEdgeReg = (word)((((Int32)getReg16(PWM_SM0_VAL1) - (Int16)getReg16(PWM_SM0_INIT) + 0x01) * (Int32)Ratio) / 0x7FFFU); /* Store value to the set duty register */

[jjt]

Digging further it appears SM1 is initialized by eFlexPWM to share SM0's clock.

Where's the best source of direction for the eFlexPWM and PWMC1 for Processor Expert for DSC 56F8256? 

[xiangjun_rong]

Hi,

Each eFlexPWM sub-module has PWM_SMnCTRL2, in the register, the CLK_SEL bits select the clock source. For the SM0 module, the CLK_SEL can select the IPBUS clock or EXT_CLK clock, the clock can be divided by the PRSC bits in PWM_SM0CTRL register and get the clock of the SM0.

For the other sub-module except SM0,they can select the Submodule 0’s clock (AUX_CLK) with CLK_SEL bits as 2b'10, in this way, all the other sub-module will use the SM0 clock which has been divided by the the PRSC bits in PWM_SM0CTRL register, so all the sub-module of eFlexPWM will be driven by the same clock.

Hope it can help you

BR

XiangJun Rong