Adding sn65dsi83 MIPI to LVDS bridge to device tree on IMX8MQ based board.

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Adding sn65dsi83 MIPI to LVDS bridge to device tree on IMX8MQ based board.

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bitglitcher
Contributor II

Hello dear IMX support team,

I was wondering how to add support for the sn65dsi83 bridge on a IMX8MQ based board. This is the old device tree that used to work on the Linux IMX 5.4 kernel.

It seems that I'm missing something because I get the following errors from the output of journalctl.

 

 imx-dcss 32e00000.display-controller: IRQ ctxld not found
 imx-dcss 32e00000.display-controller: submodules initialization failed
 nwl-dsi 30a00000.mipi_dsi: [drm:nwl_dsi_probe] Using LCDIF as input source

 

Maybe I need to also specify a missing endpoint.

 

[    1.933819] nwl-dsi 30a00000.mipi-dsi: [drm:nwl_dsi_probe] *ERROR* No valid input endpoint found
[    1.942685] nwl-dsi: probe of 30a00000.mipi-dsi failed with error -22

 

 

I saw here an example on how to setup the device tree. I saw that mine is similar with the exemption that I'm missing a port parameter. Seems that the definition changed on the new kernel source.

This is the port definition that I'm missing from my device tree. The issue here is that I don't know where &panel_in_lvds is coming from and where or how to I define one. I'm using a G1211XN01 Panel.

 

                port@2 {
                    reg = <2>;

                    endpoint {
                        remote-endpoint = <&panel_in_lvds>;
                    };

 

 

Here is the device tree that I currently have.

 

/*
 * Copyright 2017 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include "imx8mq-itx-p-c444.dts"


&irqsteer {
        status = "okay";
};

/delete-node/ &hdmi;

/ {
	bl: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm1 0 5000000 0>;
		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
				     10 11 12 13 14 15 16 17 18 19
				     20 21 22 23 24 25 26 27 28 29
				     30 31 32 33 34 35 36 37 38 39
				     40 41 42 43 44 45 46 47 48 49
				     50 51 52 53 54 55 56 57 58 59
				     60 61 62 63 64 65 66 67 68 69
				     70 71 72 73 74 75 76 77 78 79
				     80 81 82 83 84 85 86 87 88 89
				     90 91 92 93 94 95 96 97 98 99
				    100>;
		default-brightness-level = <80>;
		status = "okay";
	};

	sound-hdmi {
		status = "disabled";
	};
};

&lcdif {
        status = "disabled";
};

&dcss {
    status = "okay";
//    disp-dev = "mipi_disp";

    clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
         <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
         <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
         <&clk IMX8MQ_CLK_DC_PIXEL>,
         <&clk IMX8MQ_CLK_DUMMY>,
         <&clk IMX8MQ_CLK_DISP_DTRC>;
    clock-names = "apb", "axi", "rtrm", "pix", "pix_out", "dtrc";

    assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL>,
              <&clk IMX8MQ_CLK_DISP_AXI>,
              <&clk IMX8MQ_CLK_DISP_RTRM>,
              <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
              <&clk IMX8MQ_VIDEO_PLL1>;
    assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
                 <&clk IMX8MQ_SYS1_PLL_800M>,
                 <&clk IMX8MQ_SYS1_PLL_800M>,
                 <&clk IMX8MQ_CLK_25M>;
    assigned-clock-rates = <600000000>,
                   <800000000>,
                   <0>,
                   <400000000>,
                   <599999999>;

    port@0 {
        dcss_out: endpoint {
            remote-endpoint = <&mipi_dsi_in>;
        };
    };
};

&dphy {
	status = "okay";
};

&mipi_dsi {
	status = "okay";
	/*
	assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>,
		<&clk IMX8MQ_CLK_DSI_CORE>,
		<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
		<&clk IMX8MQ_VIDEO_PLL1>;
	assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
                <&clk IMX8MQ_SYS1_PLL_266M>,
                <&clk IMX8MQ_CLK_25M>;
	assigned-clock-rates = <24000000>,
                <266000000>,
                <0>,
                <599999999>;
	*/
	
	ports {
	        #address-cells = <1>;
	        #size-cells = <0>;
	
	        port@0 {
	               reg = <0>;
	               mipi_dsi_in: endpoint {
	                        remote-endpoint = <&dcss_out>;
	               };
	        };
	
	
		port@1 {
			reg = <1>;
			mipi_dsi_out: endpoint {
				remote-endpoint = <&lvds_bridge_in>;
			};
		};
	};

};


&i2c3 {
	dsi_lvds_bridge: sn65dsi83@2c {
		compatible = "ti,sn65dsi83";
		reg = <0x2c>;
		ti,dsi-lanes = <4>;
		ti,lvds-format = <1>;
		ti,lvds-bpp = <24>;
		ti,width-mm = <245>;
		ti,height-mm = <184>;
		enable-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lvds_bridge_en>;
		status = "okay";

		display-timings {
			native-mode = <&timing0>;
			timing0: 1024x768_60Hz {
				clock-frequency = <65000000>;
				hactive = <1024>;
				vactive = <768>;
				hback-porch = <156>;
				hfront-porch = <156>;
				vback-porch = <16>;
				vfront-porch = <16>;
				hsync-len = <8>;
				vsync-len = <6>;
				de-active = <1>;
			};
		};

		port@0 {
			lvds_bridge_in: endpoint {
				remote-endpoint = <&mipi_dsi_out>;
			};
		};
	};
};

lvds_backlight: &pwm1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_backligth_pwm1>;
};

&iomuxc {
		pinctrl_backligth_pwm1: backligth_pwm1 {
			fsl,pins = <
				/* BCKLT_PWM_3V3 */
				MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT	0x16
				/* BCKLT_EN_3V3 */
				MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3		0x59
				/* 12V_EN */
				MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2	0x59
			>;
		};

		/* Use the LVDS bridge EN Pin for the SN65DSI83 Reset */
		pinctrl_lvds_bridge_en: lvds_bridge_en {
			fsl,pins = <
				/* LVDS_EN_1V8 */
				MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23	0x16
				/* LVDS_IRQ_1V8to3V3 */
				MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24	0x16
				/* SEL68_3V3 */
				MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22	0x16
			>;
		};
};

 

 Thanks.

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massa
Contributor I

How do I add the second channel in split mode?

lvds {
compatible = "panel-lvds";
data-mapping = "vesa-24";
width-mm = <184>;
height-mm = <245>;
ports {
port@0 {
lvds_out: endpoint {
remote-endpoint = <&lvds_bridge_out>;
};
};
};

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1,410 Views
bitglitcher
Contributor II

Hello,

Look at the device tree bindings documentation. Add the second panel to port 3. That's what I would do.

Linux Kernel Documentation / devicetree / bindings / display / bridge / ti,sn65dsi83.yaml (mjmwired....

ldb.txt - Documentation/devicetree/bindings/display/imx/ldb.txt - Linux source code (v6.8) - Bootlin

 

You also have to configure ldb to dual mode.

Something similar to this. This is what I did before. But in this case, I didn't have a bridge before.

 

 

&ldb {
    primary;
    dual-mode;  /*split-mode;*/

    status = "okay";

    lvds-channel@0 {
        crtc = "ipu1-di1";
        fsl,data-mapping = "spwg";
        fsl,data-width = <18>;
        status = "okay";

        display-timings {
            native-mode = <&timing0>;
            timing0: 800x480 {
                clock-frequency = <65000000>;
                hactive = <800>;
                vactive = <480>;
                hback-porch = <96>;
                hfront-porch = <24>;
                vback-porch = <3>;
                vfront-porch = <10>;
                hsync-len = <72>;
                vsync-len = <7>;
            };
        };
    };

    lvds-channel@1 {
        crtc = "ipu2-di0";
        fsl,data-mapping = "spwg";
        fsl,data-width = <18>;
        status = "okay";

        display-timings {
            native-mode = <&timing1>;
            timing1: 800x480 {
                clock-frequency = <65000000>;
                hactive = <800>;
                vactive = <480>;
                hback-porch = <96>;
                hfront-porch = <24>;
                vback-porch = <3>;
                vfront-porch = <10>;
                hsync-len = <72>;
                vsync-len = <7>;
            };
        };
    };
};

 

 You might have to add split-mode to your bridge. idk you have to look at the device tree bindings or the driver source code.

 

&lvds_bridge {
	split-mode;
};

 

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Rita_Wang
NXP TechSupport
NXP TechSupport

Does it work well now? Which version BSP are you want to use?

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bitglitcher
Contributor II

Yes, it works now. Thanks.

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1,409 Views
massa
Contributor I

Hello,

I recently started working with DTS (Device Tree Source) files. I'm using the i.MX8MM module from Variscite, and in the DTS configuration section of the old kernel, I was able to utilize the display in the following manner:

dsi_lvds_bridge: sn65dsi84@2c {
		compatible = "ti,sn65dsi83";
		reg = <0x2c>;
		ti,dsi-lanes = <1>;
		ti,lvds-format = <1>;
		ti,lvds-bpp = <24>;
		ti,width-mm = <154>;
		ti,height-mm = <87>;
		enable-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lvds>;
		status = "okay";

		display-timings {
			lvds {
				clock-frequency = <33000000>;
				hactive = <800>;
				vactive = <480>;
				hback-porch = <40>;
				hfront-porch = <40>;
				vback-porch = <29>;
				vfront-porch = <13>;
				hsync-len = <48>;
				vsync-len = <3>;
				hsync-active = <0>;
				vsync-active = <0>;
				de-active = <1>;
				pixelclk-active = <0>;
			};
		};
        ...
        };

 To utilize a dual-channel LVDS in slip mode, the configuration required adding the term "slip-mode" and additionally "ti,lvds-channels = <2>". Currently, I'm using another kernel version with the same i.MX8MM module, but the DTS is different:

&panel_lvds {
		compatible = "panel-lvds";
		data-mapping = "jeida-24";
		width-mm = <154>;
		height-mm = <87>;

		panel-timing {
			clock-frequency = <39000000>;
			hactive = <800>;
			vactive = <480>;
			hback-porch = <40>;
			hfront-porch = <40>;
			vback-porch = <29>;
			vfront-porch = <13>;
			hsync-len = <48>;
			vsync-len = <3>;
			hsync-active = <0>;
			vsync-active = <0>;
			de-active = <1>;
			pixelclk-active = <0>;
		};
	};

 

I would like to understand if you managed to make it work with this configuration as well.

Thank you in advance.

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bitglitcher
Contributor II

I did use split mode. Dual mode or whatever it's called. Also, I used a simple-panel driver which had the timings pre-defined for my LVDS display.

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massa
Contributor I

Can you share the code please?

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bitglitcher
Contributor II

I made the following changes to the definition of my LVDS bridge. I added port2.

&i2c3 {
	dsi_lvds_bridge: sn65dsi83@2c {
		compatible = "ti,sn65dsi83";
		reg = <0x2c>;
		ti,dsi-lanes = <4>;
		ti,lvds-format = <1>;
		ti,lvds-bpp = <24>;
		ti,width-mm = <245>;
		ti,height-mm = <184>;
		enable-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lvds_bridge_en>;
		status = "okay";

		display-timings {
			native-mode = <&timing0>;
			timing0: 1024x768_60Hz {
				clock-frequency = <65000000>;
				hactive = <1024>;
				vactive = <768>;
				hback-porch = <156>;
				hfront-porch = <156>;
				vback-porch = <16>;
				vfront-porch = <16>;
				hsync-len = <8>;
				vsync-len = <6>;
				de-active = <1>;
			};
		};

		port@0 {
			lvds_bridge_in: endpoint {
				remote-endpoint = <&mipi_dsi_out>;
				data-lanes = <1 2 3 4>;
			};
		port@2 {
			lvds_bridge_out: endpoint {
				remote-endpoint = <&lvds_out>;
			};
		};
	};
};

I also added this LVDS panel definition to the device tree

lvds { 
	compatible = "panel-lvds";
	data-mapping = "vesa-24";
	width-mm = <184>;
	height-mm = <245>;
	ports {
		port@0 {
		lvds_out: endpoint {
			remote-endpoint = <&lvds_bridge_out>;
		};
	};
};

I believe that the endpoint on port 2 is not right. I'm not sure. 

[    0.255152] mxc-mipi-csi2_yav 30a70000.mipi_csi1: mipi_csi2_probe
[    0.255227] mxc-mipi-csi2_yav 30a70000.mipi_csi: Remote device at endpoint@0 XXX found
[    0.255254] mxc-mipi-csi2_yav 30a70000.mipi_csi1: lanes: 2, name: mxc-mipi-csi2.0

 Any help is welcomed, thanks.

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