ADC Clock Divide Select from the register ADC0_CFG1.

[patricio]

Hello all,

I have a FRDM-KL25Z and I am working with the ADC.

I configure the ADC_LDD component with the PE, to make it to work in continuous measuremente mode with interrupts. I save the results of the ADC conversions into an array.

The PE defines  the Clock Divide Select bits from the ADC0_CFG1 register as input clock/2 (ADIV = 01) . However I am interested to make the conversiones as fast as possible, so I change the register value manualy to input clock/1 (ADIV = 00).

I use a led pin to see the time that needs 3000 measurements by the oscilloscope, and I see that there is no difference when I change ADIV to 00.

In both cases it need 7.13ms for 3000measuremente (2.37us per measure). How is that possible? Should not be a difference when the ADC clock is changed?

Please find below my code.

And this is the interrupt routine:

Thank you in advance. Any help will be appreciated.

Aitor.

[patricio]

Thank you Marek,

BR.

[marek_neuzil · Accepted solution]

Hello,

The problem is caused by the high ADC clock frequency. There is defined a limit frequency that depend on the selected configuration of the ADC device, see for example KL25Z datasheet:

http://www.freescale.com/files/32bit/doc/data_sheet/KL25P80M48SF0.pdf?fpsp=1&WT_TYPE=Data%20Sheets&W...

There is following table:

When you set higher ADC clock frequency the behavior of the ADC device is not defined (I have already checked on the FRDM-KL2Z target board).

You can enable High-speed conversion mode, 8-bits A/D resolution and shortest sample time to achieve the fastest conversion time. See also the KL25Z reference manual for details about the ADC conversion time.

Best Regards,

Marek Neuzil