[PT200x] Vds disable window

[erichong]

Hello,

May I ask you one question regarding some effect of Vds disable window?

I'm answering to a question which is coming from Autron during the short to GND/Batt test.

And here are some questions need your advice.

Question A)

1) Assume now I'm in current hold phase and HS1 driver (Vbat for FET) repeats turning on/off. Diag is enabled.

2) At the moment when HS1 is off in the middle of hold phase, Vsrc of HS1 short to GND occurred.

3) But before expiration of filter length, HS1 is turned on again.

The question is, does the uCore detects Vds fault only after disable window time triggered by HS1 turn on command?

Question B)

I tried to understand how the disable window works for Vds monitoring in the PSC simulator but could not fine a good internal signal showing the operation of disable window. Please let me know which signal I have to monitor.

Thank you,

Eric

[philippe_meunie]

Bonjour Eric,

For Question A) the fault will not be detected as disable window has been reset when HS state has changed (according to description in application note AN12336, page 28 :

Cordially,

Philippe

[pierrecalmes]

Hi Eric,

For question B see example of signals that customer can look at on simulator:

The key is to look at the VDS counter for the dedicated High Side or Low side and teh status VDS showing when start to count and when VDS enabled (meaning disable windows is fnished)

You can load file attached to have access to the signals.

Let me know if any issue,

Regards

Pierre

[erichong]

Thank you, Pierre.

StatusVds and WindowCounterVds explain the situation.

Best Regards,

Eric