why is there TLB entry for CCSRBAR

[t_alex]

Hi,

In u-boot when displaying the registers, I saw an entry for CCSRBAR:

entry 01: V: 1 EPN 0xfe000000 RPN 0xffe000000 size:16 MiB

and u-boot code does add this entry using the macros CONFIG_SYS_CCSRBAR_DEFAULT(0xFE00_0000) and CONFIG_SYS_CCSRBAR_PHYS(0xF_FE00_0000).

Why is there a need for this? Based on the reference manual, all we need to do is to set a base value for CCSRBAR.

Address 0XF_FE00_0000 seems to have no defined global ID.

[LPP · Accepted solution]

e6500 (or e500) core has no a way besides MMU translation to access physical address space resources. Software must define MMU translation for each memory mapped resource to make it accessible to e6500 accesses.

After reset, e6500 core only provides one default TLB entry to access boot code and it allows for accesses within the highest 4 Kbytes of the low 4 Gbytes of memory. In order for the e6500 to access other local memory space resources, additional MMU TLB entries must be set up for mapping these regions.

CCSRBAR register defines base address of the configuration address space within local (physical) memory map. This region is visible internally in the processor to all functional units that need to be able to identify or create configuration transactions. However, e6500 core doesn't provide default MMU mapping for this address space. Boot software needs to configure MMU entry to enable core's access to CCSRBAR region.

>Address 0XF_FE00_0000 seems to have no defined global ID.

"Configuration registers are mapped by the windows defined by the CCSRBARs. These mappings supersede local access window mappings, so configuration registers do not appear as a target for local access windows."

Have a great day,
Pavel

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