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MPC8315/MPC8314 interrupt controller is described in MPC8315 Reference Manual, Chapter 8.
To unmask interrupt request from IRQ2 line please look SEMSR register.
Priority is configured in SMPRR_A register, the default for IRQ2 is MIXA6.
When interrupt happens, the software should read SIVCR register for interrupt vector and decode it according to Table 8-6 of MPC8315 Reference Manual.
Interrupt from IRQ2 line can be edge-triggered or level-triggered. For level-triggered interrupt user software must force external request to go to inactive state to clear interrupt request. For egde-triggered case interrupt request is cleared by writing logic "1" to corresponding field in SEPNR register. Edge or level mode is configured in SECNR register.
Here is a direct link to MPC8315 Reference Manual:
https://www.nxp.com/docs/en/reference-manual/MPC8315ERM.pdf
Have a great day,
Alexander
TIC
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