mpc8309 UCC5(HDLC2) RX not working UCCS register shows 7E Flags are being received,its 0x04,frames are discarded due to lack of buffers

[mdmuazzam]

Hi,

     I have been configuring HDLC controller for MPC8309TWR freescale board,but event register UCCE shows line is busy that's why frames are discarded due to lack of buffers.Actually my TX is working fine.

So please suggest what can be done for buffer handling.

Thanks

Muazzam(india)

[alexander_yakov · Accepted solution]

"Busy" means the current Rx buffer descriptor (RxBD), prefetched from RxBD table for data reception, is not empty - RxBD[E] bit is cleared.

The following is said in QE Reference Manual, Section 14.3.2: "If a match is detected, the HDLC controller checks the prefetched BD, and if empty, begins transferring the incoming frame to the BD’s associated buffer." So, if this buffer is not empty, "busy" condition occurs.

HDLC parameter ram, parameter "RBPTR" points to the current RxBD during frame reception. At the initialization, this parameter is equal to "RBASE", i.e. point to the first entry in RxBD table.

Have a great day,
Alexander
TIC

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[mdmuazzam]

hi,

   I have assigned my RXBD base addr to rbase.

in the same way did for tbase with base addr of TXBD,so now TX is working but RX not .

Thanks

[alexander_yakov]

Ok, run the controller, wait until the problem appears, than stop the controller by clearing ENT and ENR bits in GUMR_L register. Please do not modify anything except GUMR_L[ENT, ENR] bits. After that, please dump all UCC-related registers, parameter ram and buffer descriptors tables. Please submit me this dump for analysis.

[mdmuazzam]

Hi,

    Now HDLC controller Rx and Tx are OK,but while i do FTP file transfer then after sometime it's stopped.

[mdmuazzam]

hi ,

    Thanks for your all effort for helping me ,i got RX too. Actually i had to assign RXBD base addr to rbptr,I was actually assigning to just rbase not rbptr.so Now it's working .

Thanks :smileyhappy:

Muazzam(india)