The asleep signal of MPC8641D is uncorrected,Why?

[qiminglu]

I make a board with MPC8641D.When I debug with my board,I found the asleep signal always be high after power on reset,and the ready signal always low.I examine the DDR CLK and the Local Bus CLK with an oscilloscope,and there is no any output .I think the Device PLL of MPC8641D has some trouble in frequency locking.My sysclk is 400MHz,sys_pll is 1:4 and core_pll is 1:2.5,the power-on sequence in my borad is:

1.all power other than DDR power

2.DDR power

3.sysclk

So what happened to my board?Is there anyone can give some advice?

[ufedor]

You wrote:

> My sysclk is 400MHz

In the MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications the SYSCLK allowable range is 66-166.66 MHz ( Table 8. SYSCLK AC Timing Specifications).