T1042 can only up one core

[xichong]

the log we print in uboot:

CPU reset by self!
Initializing ddr....using fix params
total dram_size: 8589934592
6 GiB left unmapped
......Begin test ddr ram ......ok......!

dump RCW

0x0a10000c
0x0c000000
0x00000000
0x00000000
0x87000002
0x00400012
0x58106000
0x21000000
0x00000000
0x00000000
0x00000000
0x00030800
0x00000714
0xd402aa05
0x00000000
0x00000000
now spi boot
up part stamp check:-10 down part stamp check:-67
There Are No u-boot, try to load uboot from original offset :0x40000
Loading second stage boot loader .................................................................................................dump memory start :0x30000000

38 20 02 00 7c 20 01 24 7c 78 1b 78 38 00 00 02
7c 12 fb a6 7c 13 fb a6 7c 30 4a a6 7c 30 4b a6
3c 20 30 00 7c 3f 0b a6 38 80 10 b0 7c 90 63 a6
38 80 11 60 7c 91 63 a6 38 80 12 10 7c 92 63 a6
38 80 12 c0 7c 93 63 a6 38 80 13 70 7c 94 63 a6
38 80 14 1c 7c 95 63 a6 38 80 14 dc 7c 96 63 a6
38 80 15 90 7c 97 63 a6 38 80 16 40 7c 98 63 a6
38 80 16 f0 7c 9a 63 a6 38 80 17 a0 7c 9b 63 a6
38 80 18 50 7c 9c 63 a6 38 80 19 00 7c 9d 63 a6
38 80 19 b0 7c 9e 63 a6 38 80 1a 60 7c 9f 63 a6
38 00 00 00 3c 20 ff ff 7c 16 03 a6 7c 1c 43 a6
7c 1d 43 a6 7c 30 53 a6 7c 14 53 a6 7c 1e 0b a6
7c 1c 8b a6 7c 01 03 a6 7c 15 53 a6 3c 00 80 00
60 00 00 80 7c 10 fb a6 3c 00 01 40 60 00 02 01
7c 15 fb a6 48 00 00 05 7c 28 02 a6 38 40 00 00
7c 56 9b a6 4c 00 01 2c 7c 00 04 ac 7c 00 0f 24

U-Boot 2019.04-rc4-svn63608 (Aug 19 2022 - 16:36:10 +0800)

CPU0: T1042, Version: 1.1, (0x85200211)
Core: e5500, Version: 2.1, (0x80241021)
Clock Configuration:
CPU0:1200 MHz, CPU1:1200 MHz, CPU2:1200 MHz, CPU3:1200 MHz,
CCB:500 MHz,
DDR:800 MHz (1600 MT/s data rate) (Asynchronous), IFC:250 MHz
QE:250 MHz
FMAN1: 500 MHz
QMAN: 250 MHz
PME: 250 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 0a10000c 0c000000 00000000 00000000
00000010: 87000002 00400012 58106000 21000000
00000020: 00000000 00000000 00000000 00030800
00000030: 00000714 d402aa05 00000000 00000000
Board: T1042RDB
Board rev: 0xff CPLD ver: 0xff, vBank: 7
I2C: ready
DRAM: 6 GiB left unmapped
2 GiB (DDR4, 64-bit, CL=12, ECC off)
L2: 256 KiB enabled
Corenet Platform Cache: 256 KiB enabled
Using SERDES1 Protocol: 135 (0x87)
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 294
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 294
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 294
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 294
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 294
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 294
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 294
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 294
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 294
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 292 table addr=0x7FF24100
cpu_up_mask=0x1 line 294
CPU up timeout. CPU up mask is 1 should be f
MMC: FSL_SDHC: 0
Loading Environment from SPI Flash... SF: Detected n25q128a13 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
*** Warning - bad CRC, using default environment

In: serial
Out: serial
Err: serial

can anyone help to figure out why core 1,2 3 can't be up?

[xichong]

Hi,

We have checked the power supply/clock/ power sequence/ POR configuration and all are comply with the datasheet.

We also checked the ddr4 memory in Linux boot, with large file read/write without error.

Actually this is a redesign card which replace ddr3l with ddr4， and enlarge from 4GB to 8GB, the others keep the same( we change the G1VDD supply to 1.2V and cfg_dram_type to ddr4).

Unfortunately, we don't have CodeWarrior+CodeWarrior TAP.

Here is the output of cpu status:

=> cpu status
table base @ 0x3ff24100
Running on cpu 0

table @ 0x3ff24140
addr - 0x00000000
r3 - 0x00000000
pir - 0x00000000
Running on cpu 0

table @ 0x3ff24180
addr - 0x00000000
r3 - 0x00000000
pir - 0x00000000
Running on cpu 0

table @ 0x3ff241c0
addr - 0x00000000
r3 - 0x00000000
pir - 0x00000000
=>

And in linux boot, it will print :

e500 family performance monitor hardware support registered
Processor 1 is stuck.
Processor 2 is stuck.
Processor 3 is stuck.
Brought up 1 CPUs

Since we have checked all the possibility in hardware side, we doubt if it was caused by UBOOT? 

Looking forward for your reply.

BR,

Xichong Chen

[yipingwang]

I uploaded SDK 2.0 u-boot source code to the following link.

链接: https://pan.baidu.com/s/1DefSoiWswLt1c_ogFbmfUA?pwd=9efa 提取码: 9efa

Please modify u-boot source code according to your custom board, then build u-boot image and verify it on your target board.

[xichong · Accepted solution]

Thanks, we have resolved the problem. It's due to the DM/DBI setting in DDR4.

[yipingwang]

Under u-boot prompt, please use the command "cpu <num> status" to check whether the processor is running.

If the CPU doesn't run, please check the probable hardware cause.

Core power supply failure       

Improper processor connection, please refer to the design checklist which could be downloaded from NXP public Website.

Incorrect timing of POR configuration signal(s), please refer to Power on reset initialization section in the processor reference manual.

If processors run normally, please check DDR memory, please enable "mtest" in u-boot to do more test on DDR memory.

If you have CodeWarrior+CodeWarrior TAP, please configure your target board as hard-coded RCW, then create a SRAM CodeWarrior bareboard project and select "Core 1" at "Core index", then verify whether CW project can run on Core 1.