T1042 PCIe Gen1 Link width intermittence

[brian_bogdan]

Hi,

We have an embedded design with a T1042 PQIII connected to a PCIe switch running x4 gen1 speeds.   We intermittently see the link come up as a x2 instead of a x4.  This is about 1 in 100 power cycles only.

I read thru the Link Init & training section of PCIe standard,  which was helpful understanding the steps involved in bring up the Link.  I found PEX_LTSSM_STAT register which tell you which state is active, but is there a way to find out the results of each sub state?  I'm curious at what state did the x2 get determined (i.e. Detect, Polling, or Configuration)

We have checked the PCIe signal integrity (TX and RX directions), on another board and the eye very open.  I'm not able to probe this intermittent board at the moment, but I feel confident that this is not a signal integrity issue.

Any other advise on how to locate what is causing this will be appreciated.

Thanks

Brian

[brian_bogdan]

Hi,

Thanks for quick reply.  I have collected answers to your questions in attached file.  I also copied parts of the schematic if my words are not clear.

Thanks

Brian

[brian_bogdan]

I'm not sure if my attachment was included.  try #2.

[brian_bogdan]

Third attempt to attach my responses

Thanks

Brian

[ufedor]

> Summary: caps are close in value, but we have bead instead of 0.33 ohm

It is a must to implement the AVDD filter using resistor as shown in the Design Checklist.

[brian_bogdan]

HI,

We have not been able to recreate this issue, even after 100's of power cycles.    We are moving the setup into a temp chamber to see if that will recreate the issue.  Once, recreated, we will test the 0.33 ohm resistor.

Another item we noticed when coming up incorrectly in the x2 lane configuration is these asserts:

pcieport 0001:00:00.0: AER: Multiple Corrected error received: id=0000

pcieport 0001:00:00.0: PCIe Bus Error: severity=Corrected, type=Physical Layer, id=0000(Receiver ID)
pcieport 0001:00:00.0: device [1957:0824] error status/mask=00000001/00002000
pcieport 0001:00:00.0: [ 0] Receiver Error (First)

These appear to be physical layer issues and wevwould like to know if we can get more information on what type of physical layer issues?  We have probed these lanes (on another board) and the eye was very open (>400mVPP), so I would not believe it is SI issue.  Is there any registers that can be captured when (if) the failure occurs again?

Also, We are starting to notice these PCIePORT asserts on other boards.  Now this issue has been discussed with other engineers and people are looking for it, but its still a very rare in occurrences and not reproducible.  We are in the process of connecting a scope up to the PXIe lanes on verify eye opening/jitter.

Any further recommendation appreciated.

Thanks

Brian

[brian_bogdan]

Hi,

Is there any response to my last reply?

Brian

[ufedor]

Please ensure that analog supply filters of SerDes PLLs are implemented exactly as recommended.

[brian_bogdan]

HI,

We located a circuit board that would exhibit the prior mention PCIePORT asserts.    We changed the Serdes PLL power supply filter to match as recommended (AN4825).  For AVDD_SD1_PLL1, we changed the bead to 0.33 ohm resistor and the HF cap from 0.1uf to 0.003uf.   We repeated the 10 power cycles and obtain the same PCIEPORT asserts.  So, it does not appear to be related to the power supply filtering. 

What is the next step to understand these asserts?   

FYI, We also have captured the PCIe serdes eye measurement for this circuit board and checked the jitter on the T1042 reference clocks.  I can provide if needed, but these all appear to be good.

thanks

Brian

[ufedor]

It will be convenient to create a Technical Case (using https://support.nxp.com/s) so it will contain:

- the latest processor connection schematics as PDF

- detailed issue description and reproducibility environments and steps

- eye diagrams for each lane of the PCIe link

- PCIe analyzer trace containing the link training with incorrect width

- U-Boot booting logs corresponding to correct and incorrect PCIe link widths

[brian_bogdan]

HI,

I created a technical case:  00320460.  I will respond to your questions under that case.

Brian Bogdan

[brian_bogdan]

Hi,

Is there any response to my last reply?

Brian

[ufedor]

Points to check:

1) AC coupling capacitors are 100nF

2) T1042 SerDes powering is implemented as recommended in the processor's Design Checklist.

Ensure that analog supply filters of SerDes PLLs are implemented exactly as recommended.

3) Ensure that if PLL2 is not used, then it is explicitly powered down in the RCW.