Setting up DDR3l for t1042

megaloldeanmega · ‎08-30-2018

Hello, I'm trying to configure DDR3l on the T1042. Attach pdf for DDR3l - AS4C512M16D3L. (4 DDR3l + 1 DDR3l for ECC).

To create a .tcl script I use QorlQ Configuration Project.

1) Question - DRAM configuration - 2GB: 512 x 4?

2) Question - parametr DDR3l controller are true?

3) Question (the most difficult to understand) - length of lines ? This is the length of the line from CLK from DQS ?

Developers of our site provided me with data:

DQS0 58.793/58.399
DQS1 60.073/60.308
DQS2 50.51/50.213
DQS3 47.891/48.06
DQS4 30.003/29.952
DQS5 31.789/32.076
DQS6 28.033/27.944
DQS7 28.345/29.347
DQS8 44.222/43.724

CLK 47.05 + 14.8 + 15.03 + 15.96 + 16.08

I entered: 58 60 50 48 30 31 28 29 44 and get .tcl script^

###############################################################################
## Target initialization file - DDR controller 1 section #
##
## Copyright : 2016 NXP, Inc. All Rights Reserved.
## SOURCE DISTRIBUTION PERMISSIBLE as directed in End User License Agreement.
##
## http : www.nxp.com
## mail : support@nxp.com
################################################################################

proc value_of {x} {
return $x
}

# DDR Controller 1 Registers

# DDR_SDRAM_CFG
mem i:0xFE008110 = [value_of 0x67200008]

# CS0_BNDS
mem i:0xFE008000 = [value_of 0x7F]

# CS1_BNDS
mem i:0xFE008008 = [value_of 0x008000BF]

# CS2_BNDS
mem i:0xFE008010 = [value_of 0x0100013F]

# CS3_BNDS
mem i:0xFE008018 = [value_of 0x0140017F]

# CS0_CONFIG
mem i:0xFE008080 = [value_of 0x80014302]

# CS1_CONFIG
mem i:0xFE008084 = [value_of 0x0202]

# CS2_CONFIG
mem i:0xFE008088 = [value_of 0x0202]

# CS3_CONFIG
mem i:0xFE00808C = [value_of 0x0202]

# CS0_CONFIG_2
mem i:0xFE0080C0 = [value_of 0x00]

# CS1_CONFIG_2
mem i:0xFE0080C4 = [value_of 0x00]

# CS2_CONFIG_2
mem i:0xFE0080C8 = [value_of 0x00]

# CS3_CONFIG_2
mem i:0xFE0080CC = [value_of 0x00]

# TIMING_CFG_3
mem i:0xFE008100 = [value_of 0x01071000]

# TIMING_CFG_0
mem i:0xFE008104 = [value_of 0x4055000C]

# TIMING_CFG_1
mem i:0xFE008108 = [value_of 0xBCB48E66]

# TIMING_CFG_2
mem i:0xFE00810C = [value_of 0x00411118]

# DDR_SDRAM_CFG_2
mem i:0xFE008114 = [value_of 0x00401050]

# DDR_SDRAM_MODE
mem i:0xFE008118 = [value_of 0x00061C71]

# DDR_SDRAM_MODE_2
mem i:0xFE00811C = [value_of 0x00180000]

# DDR_SDRAM_MODE_3
mem i:0xFE008200 = [value_of 0x00]

# DDR_SDRAM_MODE_4
mem i:0xFE008204 = [value_of 0x00]

# DDR_SDRAM_MODE_5
mem i:0xFE008208 = [value_of 0x00]

# DDR_SDRAM_MODE_6
mem i:0xFE00820C = [value_of 0x00]

# DDR_SDRAM_MODE_7
mem i:0xFE008210 = [value_of 0x00]

# DDR_SDRAM_MODE_8
mem i:0xFE008214 = [value_of 0x00]

# DDR_SDRAM_MD_CNTL
mem i:0xFE008120 = [value_of 0x00000000]

# DDR_SDRAM_INTERVAL
mem i:0xFE008124 = [value_of 0x18600618]

# DDR_DATA_INIT
mem i:0xFE008128 = [value_of 0xDEADBEEF]

# DDR_SDRAM_CLK_CNTL
mem i:0xFE008130 = [value_of 0x02800000]

# DDR_INIT_ADDR
mem i:0xFE008148 = [value_of 0x00000000]

# DDR_INIT_EXT_ADDR
mem i:0xFE00814C = [value_of 0x00000000]

# TIMING_CFG_4
mem i:0xFE008160 = [value_of 0x00220001]

# TIMING_CFG_5
mem i:0xFE008164 = [value_of 0x04401400]

# DDR_ZQ_CNTL
mem i:0xFE008170 = [value_of 0x89080600]

# DDR_WRLVL_CNTL
mem i:0xFE008174 = [value_of 0x8655F608]

# DDR_SR_CNTR
mem i:0xFE00817C = [value_of 0x00000000]

# DDR_WRLVL_CNTL_2
mem i:0xFE008190 = [value_of 0x08080806]

# DDR_WRLVL_CNTL_3
mem i:0xFE008194 = [value_of 0x06060607]

# DDR_ERR_DISABLE
mem i:0xFE008E44 = [value_of 0x00]

# DDR_ERR_INT_EN
mem i:0xFE008E48 = [value_of 0x1D]

# DDR_ERR_SBE
mem i:0xFE008E58 = [value_of 0x00010000]

# DDRCDR_1
mem i:0xFE008B28 = [value_of 0x80040000]

# DDRCDR_2
mem i:0xFE008B2C = [value_of 0x01]

# DDR_SDRAM_CFG_3
mem i:0xFE008260 = [value_of 0x00]

# TIMING_CFG_6
mem i:0xFE008168 = [value_of 0x00]

# TIMING_CFG_7
mem i:0xFE00816C = [value_of 0x00]

# TIMING_CFG_8
mem i:0xFE008250 = [value_of 0x00]

# DESKEW_CNTL
mem i:0xFE0082A0 = [value_of 0x00]

# DQ_MAP0
mem i:DDRmc1_DQ_MAP0_ADDR = [value_of 0x00]

# DQ_MAP1
mem i:DDRmc1_DQ_MAP1_ADDR = [value_of 0x00]

# DQ_MAP2
mem i:DDRmc1_DQ_MAP2_ADDR= [value_of 0x00]

# DQ_MAP3
mem i:DDRmc1_DQ_MAP3_ADDR = [value_of 0x00]

# DDR_SDRAM_MODE_9
mem i:0xFE008220 = [value_of 0x00]

# DDR_SDRAM_MODE_10
mem i:0xFE008224 = [value_of 0x00]

# DDR_SDRAM_MODE_11
mem i:0xFE008228 = [value_of 0x00]

# DDR_SDRAM_MODE_12
mem i:0xFE00822C = [value_of 0x00]

# DDR_SDRAM_MODE_13
mem i:0xFE008230 = [value_of 0x00]

# DDR_SDRAM_MODE_14
mem i:0xFE008234 = [value_of 0x00]

# DDR_SDRAM_MODE_15
mem i:0xFE008238 = [value_of 0x00]

# DDR_SDRAM_MODE_16
mem i:0xFE00823C = [value_of 0x00]

# DDR_SDRAM_RCW_3
mem i:0xFE0081A0 = [value_of 0x00]

# DDR_SDRAM_RCW_4
mem i:0xFE0081A4 = [value_of 0x00]

# DDR_SDRAM_RCW_5
mem i:0xFE0081A8 = [value_of 0x00]

# DDR_SDRAM_RCW_6
mem i:0xFE0081AC = [value_of 0x00]

#Delay before enable
wait 500

#DDR_SDRAM_CFG
mem i:0xFE008110 = [value_of 0xE7200008]

# wait for DRAM data initialization
wait 1000

Part of this script I'm inserting in T1042RDB_init_core.tcl:

########################################################################################
# Initialization file for T1042 RDB
# Clock Configuration:
# CPU: 1400 MHz, CCB: 600 MHz,
# DDR: 1600 MHz, IFC: 150 MHz,
# FMAN1: 600 MHz, QMAN: 300 MHz, PME: 300 MHz
########################################################################################

# Choose which core will initialize the board
variable master_core 0

variable CCSRBAR 0xFE000000

proc CCSR_ADDR {reg_off} {
global CCSRBAR

return i:0x[format %x [expr {$CCSRBAR + $reg_off}]]
}

proc init_board {} {

# disable Boot Space Translation
mem [CCSR_ADDR 0x28] = 0x00000000

##################################################################################
# Local Access Windows Setup

# LAW0 to IFC (NOR) - 128MB
mem [CCSR_ADDR 0xc00] = 0x00000000
mem [CCSR_ADDR 0xc04] = 0xE8000000
mem [CCSR_ADDR 0xc08] = 0x81F0001A

# LAW1 to IFC (CPLD) - 4KB
mem [CCSR_ADDR 0xc10] = 0x00000000
mem [CCSR_ADDR 0xc14] = 0xFFDF0000
mem [CCSR_ADDR 0xc18] = 0x81F0000B

# LAW2 to DCSR - 4MB
mem [CCSR_ADDR 0xc20] = 0x00000000
mem [CCSR_ADDR 0xc24] = 0xF0000000
mem [CCSR_ADDR 0xc28] = 0x81D00015

# LAW4 to CCSR - 12M
mem [CCSR_ADDR 0xc40] = 0x00000000
mem [CCSR_ADDR 0xc44] = 0xfe000000
mem [CCSR_ADDR 0xc48] = 0x81e00013

# LAW3 to IFC (NAND) - 1MB
mem [CCSR_ADDR 0xc30] = 0x00000000
mem [CCSR_ADDR 0xc34] = 0xFF800000
mem [CCSR_ADDR 0xc38] = 0x81F00013

# LAW15 to DDR (Memory Complex 1) - 2GB
mem [CCSR_ADDR 0xcf0] = 0x00000000
mem [CCSR_ADDR 0xcf4] = 0x00000000
mem [CCSR_ADDR 0xcf8] = 0x8100001E

##################################################################################
# DDR Controller Setup

proc value_of {x} {
return $x
}

# DDR Controller 1 Registers

# DDR_SDRAM_CFG
mem i:0xFE008110 = [value_of 0x67200008]

# CS0_BNDS
mem i:0xFE008000 = [value_of 0x7F]

# CS1_BNDS
mem i:0xFE008008 = [value_of 0x008000BF]

# CS2_BNDS
mem i:0xFE008010 = [value_of 0x0100013F]

# CS3_BNDS
mem i:0xFE008018 = [value_of 0x0140017F]

# CS0_CONFIG
mem i:0xFE008080 = [value_of 0x80014302]

# CS1_CONFIG
mem i:0xFE008084 = [value_of 0x0202]

# CS2_CONFIG
mem i:0xFE008088 = [value_of 0x0202]

# CS3_CONFIG
mem i:0xFE00808C = [value_of 0x0202]

# CS0_CONFIG_2
mem i:0xFE0080C0 = [value_of 0x00]

# CS1_CONFIG_2
mem i:0xFE0080C4 = [value_of 0x00]

# CS2_CONFIG_2
mem i:0xFE0080C8 = [value_of 0x00]

# CS3_CONFIG_2
mem i:0xFE0080CC = [value_of 0x00]

# TIMING_CFG_3
mem i:0xFE008100 = [value_of 0x01071000]

# TIMING_CFG_0
mem i:0xFE008104 = [value_of 0x4055000C]

# TIMING_CFG_1
mem i:0xFE008108 = [value_of 0xBCB48E66]

# TIMING_CFG_2
mem i:0xFE00810C = [value_of 0x00411118]

# DDR_SDRAM_CFG_2
mem i:0xFE008114 = [value_of 0x00401050]

# DDR_SDRAM_MODE
mem i:0xFE008118 = [value_of 0x00061C71]

# DDR_SDRAM_MODE_2
mem i:0xFE00811C = [value_of 0x00180000]

# DDR_SDRAM_MODE_3
mem i:0xFE008200 = [value_of 0x00]

# DDR_SDRAM_MODE_4
mem i:0xFE008204 = [value_of 0x00]

# DDR_SDRAM_MODE_5
mem i:0xFE008208 = [value_of 0x00]

# DDR_SDRAM_MODE_6
mem i:0xFE00820C = [value_of 0x00]

# DDR_SDRAM_MODE_7
mem i:0xFE008210 = [value_of 0x00]

# DDR_SDRAM_MODE_8
mem i:0xFE008214 = [value_of 0x00]

# DDR_SDRAM_MD_CNTL
mem i:0xFE008120 = [value_of 0x00000000]

# DDR_SDRAM_INTERVAL
mem i:0xFE008124 = [value_of 0x18600618]

# DDR_DATA_INIT
mem i:0xFE008128 = [value_of 0xDEADBEEF]

# DDR_SDRAM_CLK_CNTL
mem i:0xFE008130 = [value_of 0x02800000]

# DDR_INIT_ADDR
mem i:0xFE008148 = [value_of 0x00000000]

# DDR_INIT_EXT_ADDR
mem i:0xFE00814C = [value_of 0x00000000]

# TIMING_CFG_4
mem i:0xFE008160 = [value_of 0x00220001]

# TIMING_CFG_5
mem i:0xFE008164 = [value_of 0x04401400]

# DDR_ZQ_CNTL
mem i:0xFE008170 = [value_of 0x89080600]

# DDR_WRLVL_CNTL
mem i:0xFE008174 = [value_of 0x8655F608]

# DDR_SR_CNTR
mem i:0xFE00817C = [value_of 0x00000000]

# DDR_WRLVL_CNTL_2
mem i:0xFE008190 = [value_of 0x08080806]

# DDR_WRLVL_CNTL_3
mem i:0xFE008194 = [value_of 0x06060607]

# DDR_ERR_DISABLE
mem i:0xFE008E44 = [value_of 0x00]

# DDR_ERR_INT_EN
mem i:0xFE008E48 = [value_of 0x1D]

# DDR_ERR_SBE
mem i:0xFE008E58 = [value_of 0x00010000]

# DDRCDR_1
mem i:0xFE008B28 = [value_of 0x80040000]

# DDRCDR_2
mem i:0xFE008B2C = [value_of 0x01]

# DDR_SDRAM_CFG_3
mem i:0xFE008260 = [value_of 0x00]

# TIMING_CFG_6
mem i:0xFE008168 = [value_of 0x00]

# TIMING_CFG_7
mem i:0xFE00816C = [value_of 0x00]

# TIMING_CFG_8
mem i:0xFE008250 = [value_of 0x00]

# DESKEW_CNTL
mem i:0xFE0082A0 = [value_of 0x00]

# DQ_MAP0
mem i:0xFE008400 = [value_of 0x00]

# DQ_MAP1
mem i:0xFE008404 = [value_of 0x00]

# DQ_MAP2
mem i:0xFE008408= [value_of 0x00]

# DQ_MAP3
mem i:0xFE008400 = [value_of 0x00]

# DDR_SDRAM_MODE_9
mem i:0xFE008220 = [value_of 0x00]

# DDR_SDRAM_MODE_10
mem i:0xFE008224 = [value_of 0x00]

# DDR_SDRAM_MODE_11
mem i:0xFE008228 = [value_of 0x00]

# DDR_SDRAM_MODE_12
mem i:0xFE00822C = [value_of 0x00]

# DDR_SDRAM_MODE_13
mem i:0xFE008230 = [value_of 0x00]

# DDR_SDRAM_MODE_14
mem i:0xFE008234 = [value_of 0x00]

# DDR_SDRAM_MODE_15
mem i:0xFE008238 = [value_of 0x00]

# DDR_SDRAM_MODE_16
mem i:0xFE00823C = [value_of 0x00]

# DDR_SDRAM_RCW_3
mem i:0xFE0081A0 = [value_of 0x00]

# DDR_SDRAM_RCW_4
mem i:0xFE0081A4 = [value_of 0x00]

# DDR_SDRAM_RCW_5
mem i:0xFE0081A8 = [value_of 0x00]

# DDR_SDRAM_RCW_6
mem i:0xFE0081AC = [value_of 0x00]

#Delay before enable
wait 500

#DDR_SDRAM_CFG
mem i:0xFE008110 = [value_of 0xE7200008]

# wait for DRAM data initialization
wait 1000

##################################################################################
# eSPI Setup
# SPMODE
mem [CCSR_ADDR 0x110000] = 0x80000403
# SPIM - catch all events
mem [CCSR_ADDR 0x110008] = 0x00000000
# SPMODE0
mem [CCSR_ADDR 0x110020] = 0x2E170008

##################################################################################
# IFC Controller Setup

set NOR_CS 0
set NAND_CS 1
set CPLD_CS 2

# CPLD, addr 0xFFDF0000, 4KB size, 8-bit, GPCM, Valid
# CSPR_EXT
mem [CCSR_ADDR [expr {0x12400C + $CPLD_CS * 0x0C}]] = 0x00000000
# CSPR
mem [CCSR_ADDR [expr {0x124010 + $CPLD_CS * 0x0C}]] = 0xFFDF0085
# AMASK
mem [CCSR_ADDR [expr {0x1240A0 + $CPLD_CS * 0x0C}]] = 0xFFFF0000
# CSOR
mem [CCSR_ADDR [expr {0x124130 + $CPLD_CS * 0x0C}]] = 0x00000000

# IFC_FTIM0
mem [CCSR_ADDR [expr {0x1241C0 + $CPLD_CS * 0x30}]] = 0xE00E000E
# IFC_FTIM1
mem [CCSR_ADDR [expr {0x1241C4 + $CPLD_CS * 0x30}]] = 0x0E001F00
# IFC_FTIM2
mem [CCSR_ADDR [expr {0x1241C8 + $CPLD_CS * 0x30}]] = 0x0E00001F
# IFC_FTIM3
mem [CCSR_ADDR [expr {0x1241CC + $CPLD_CS * 0x30}]] = 0x00000000

# NOR Flash, addr 0xE8000000, 128MB size, 16-bit NOR
# CSPR_EXT
mem [CCSR_ADDR [expr {0x12400C + $NOR_CS * 0x0C}]] = 0x00000000
# CSPR
mem [CCSR_ADDR [expr {0x124010 + $NOR_CS * 0x0C}]] = 0xE8000101
# AMASK
mem [CCSR_ADDR [expr {0x1240A0 + $NOR_CS * 0x0C}]] = 0xF8000000
# CSOR
mem [CCSR_ADDR [expr {0x124130 + $NOR_CS * 0x0C}]] = 0x0000000C

# IFC_FTIM0
mem [CCSR_ADDR [expr {0x1241C0 + $NOR_CS * 0x30}]] = 0x40050005
# IFC_FTIM1
mem [CCSR_ADDR [expr {0x1241C4 + $NOR_CS * 0x30}]] = 0x35001A13
# IFC_FTIM2
mem [CCSR_ADDR [expr {0x1241C8 + $NOR_CS * 0x30}]] = 0x0410381C
# IFC_FTIM3
mem [CCSR_ADDR [expr {0x1241CC + $NOR_CS * 0x30}]] = 0x00000000

# NAND Flash, addr 0xFF800000, 64KB size, 8-bit NAND
# CSPR_EXT
mem [CCSR_ADDR [expr {0x12400C + $NAND_CS * 0x0C}]] = 0x00000000
# CSPR
mem [CCSR_ADDR [expr {0x124010 + $NAND_CS * 0x0C}]] = 0xFF800083
# AMASK
mem [CCSR_ADDR [expr {0x1240A0 + $NAND_CS * 0x0C}]] = 0xFFFF0000
# CSOR
mem [CCSR_ADDR [expr {0x124130 + $NAND_CS * 0x0C}]] = 0x0110A100

# IFC_FTIM0
mem [CCSR_ADDR [expr {0x1241C0 + $NAND_CS * 0x30}]] = 0x0E18070A
# IFC_FTIM1
mem [CCSR_ADDR [expr {0x1241C4 + $NAND_CS * 0x30}]] = 0x32390E18
# IFC_FTIM2
mem [CCSR_ADDR [expr {0x1241C8 + $NAND_CS * 0x30}]] = 0x01E0501E
# IFC_FTIM3
mem [CCSR_ADDR [expr {0x1241CC + $NAND_CS * 0x30}]] = 0x00000000
}

proc T1042RDB_init_core {} {
global master_core

variable CAM_GROUP "regPPCTLB1/"
variable SPR_GROUP "e5500 Special Purpose Registers/"
variable GPR_GROUP "General Purpose Registers/"
##################################################################################
#
# Memory Map
#
# 0x00000000 0x7FFFFFFF DDR 2 GB
# 0xE0000000 0xEFFFFFFF NOR 256 MB
# 0xF0000000 0xF03FFFFF DCSR 4 MB
# 0xFE000000 0xFEFFFFFF CCSR Space 16 MB
# 0xFF800000 0xFF8FFFFF NAND 1 MB
# 0xFFDF0000 0xFFDF0FFF CPLD 4 KB
# 0xFFFFF000 0xFFFFFFFF Boot Page 4 KB
#
##################################################################################

##################################################################################
# MMU initialization

# define 16MB TLB entry 1 : 0xFE000000 - 0xFEFFFFFF for CCSR cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM1 = 0x7000000A1C08000000000000FE00000000000000FE000001

# define 256MB TLB entry 2 : 0xE0000000 - 0xEFFFFFFF for NOR cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM2 = 0x9000000A1C08000000000000E000000000000000E0000001

# define 1GB TLB entry 3 : 0x00000000 - 0x3FFFFFFF for DDR cache inhibited
reg ${CAM_GROUP}L2MMU_CAM3 = 0xA00000081C08000000000000000000000000000000000001

# define 1GB TLB entry 4 : 0x40000000 - 0x7FFFFFFF for DDR cache inhibited
reg ${CAM_GROUP}L2MMU_CAM4 = 0xA00000081C08000000000000400000000000000040000001

# define 4MB TLB entry 5 : 0xF0000000 - 0xF03FFFFF for DCSR cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM5 = 0x6000000A1C08000000000000F000000000000000F0000001

# define 4KB TLB entry 6 : 0xFFDF0000 - 0xFFDF0FFF for CPLD cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM6 = 0x1000000A1C08000000000000FFDF000000000000FFDF0001

# define 1MB TLB entry 7 : 0xFF800000 - 0xFF8FFFFF for NAND cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM7 = 0x5000000A1C08000000000000FF80000000000000FF800001

# init board, only when the init is run for master core
variable proc_id [expr {[reg ${SPR_GROUP}PIR %d -np] >> 5 }]
if {$proc_id == $master_core} {
init_board
}

##################################################################################
# Interrupt vectors initialization
# interrupt vectors in RAM at 0x[expr {${proc_id} << 1}]0000000
# IVPR (default reset value)
reg ${SPR_GROUP}IVPR = 0x[expr {${proc_id} << 1}]0000000

# interrupt vector offset registers
# IVOR0 - critical input
reg ${SPR_GROUP}IVOR0 = 0x00000100
# IVOR1 - machine check
reg ${SPR_GROUP}IVOR1 = 0x00000200
# IVOR2 - data storage
reg ${SPR_GROUP}IVOR2 = 0x00000300
# IVOR3 - instruction storage
reg ${SPR_GROUP}IVOR3 = 0x00000400
# IVOR4 - external input
reg ${SPR_GROUP}IVOR4 = 0x00000500
# IVOR5 - alignment
reg ${SPR_GROUP}IVOR5 = 0x00000600
# IVOR6 - program
reg ${SPR_GROUP}IVOR6 = 0x00000700
# IVOR7 - floating point unavailable
reg ${SPR_GROUP}IVOR7 = 0x00000800
# IVOR8 - system call
reg ${SPR_GROUP}IVOR8 = 0x00000C00
# IVOR10 - decrementer
reg ${SPR_GROUP}IVOR10 = 0x00000900
# IVOR11 - fixed-interval timer interrupt
reg ${SPR_GROUP}IVOR11 = 0x00000F00
# IVOR12 - watchdog timer interrupt
reg ${SPR_GROUP}IVOR12 = 0x00000B00
# IVOR13 - data TLB errror
reg ${SPR_GROUP}IVOR13 = 0x00001100
# IVOR14 - instruction TLB error
reg ${SPR_GROUP}IVOR14 = 0x00001000
# IVOR15 - debug
reg ${SPR_GROUP}IVOR15 = 0x00001500
# IVOR35 - performance monitor
reg ${SPR_GROUP}IVOR35 = 0x00001900

##################################################################################
# Enable branch prediction
reg ${SPR_GROUP}BUCSR = 0x01400201

##################################################################################
# Debugger settings

# enable machine check
reg ${SPR_GROUP}HID0 = 0x80000000

# enable floating point
reg ${SPR_GROUP}MSR = 0x00002000

# infinite loop at program exception to prevent taking the exception again
mem v:0x${proc_id}0000700 = 0x48000000

# prevent stack unwinding at entry_point/reset when stack pointer is not initialized
reg ${GPR_GROUP}SP = 0x0000000F

if {$proc_id == $master_core} {
# DCFG_BRR - enable all cores
mem [CCSR_ADDR 0xe00e4] = 0x0000000F
# RCPM_CTBENR - enable all cores' timebase
mem [CCSR_ADDR 0xe2084] = 0x0000000F
}
}

proc envsetup {} {
# Environment Setup
radix x
config hexprefix 0x
config MemIdentifier v
config MemWidth 32
config MemAccess 32
config MemSwap off
}

#-------------------------------------------------------------------------------
# Main
#-------------------------------------------------------------------------------

envsetup

T1042RDB_init_core

Farther attach > reset > source %scritp%. As can be seen from the code ddr mapped 0x0 . I read 0x0 ( mem 0x0) and see error:

Error reading memory

[CCS last error: Scan timeout]

athershehzad · ‎11-23-2018

@megaloldean megaloldean We are also facing similar issue
Please guide us if you have solved the problem
Also please suggest how have you entered the skews values? Is this the length of data strobe signals or the difference in length between clock and data strobe ?

Regards

yipingwang · ‎09-11-2018

Hello megaloldean megaloldean ,

I explain something about how to use DDRv tool.

If there is SPD on the target board, the user can use reading from SPD method to create and initial QCVS DDR project. If there is no SPD, the user needs to create a default QCVS project, then fill DDR related properties according to DDR data sheet to generate the initial DDR controller configuration parameters.

Then use DDRv tool to connect to the target board to do optimization and validation, the user needs to complete "Centering the clock", "Read ODT and driver" and "Write ODT and dirver" validations to get the final optimized DDR controller configuration parameters.

For detailed usage, please refer to https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.nxp.com%2Fdocs%2Fen%2Fuser-gu...

After validation with DDRv in QCVS project, please regenerate DDR configuration script from Project->Generate Processor Expert code, then use DDR controller configuration parameters in script ddrCtrl_1.py in u-boot or DDR initialization file.

The customer could refer to this document https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fcommunity.nxp.com%2Fdocs%2FDOC-33....

Have a great day,
TIC

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megaloldeanmega · ‎09-16-2018

Thank you Yiping Wang.
I ran into the problem with validation. I use codewarrior tap (usb) and when validating the validation, all cells indicate an error. Error in each cell - D_INIT was not cleared by hardware!

I noticed that in CCS always: CCSAPI connection #1 from %my_machine_name% closed

How can I correct these errors and pass validation?

EmbEng · ‎11-09-2018

- D_INIT was not cleared by hardware!

megaloldeanmegaloldean‌ were you able to solve this problem? We are stuck at same point.

Setting up DDR3l for t1042

Setting up DDR3l for t1042

Clocking

DDR