P3041: EEPROM firmware problem

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P3041: EEPROM firmware problem

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Contributor I

I have a P3041ds board which has a problem with the firmware of an EEPROM chip.

The following listing is produced by the UBOOT terminal. As you can see the EEPROM

ID is : EEPROM: Invalid ID (ff ff ff ff) instead of EEPROM: NXID v1.

Is it possible to reprogram the EEPROM  to restore it to factory default state?.

Or do I have a brick ? 

Below I have two boards one with the EEPROM problem and the other functions correctly.

(I listed both boards for comparisons)

 

------------------------------------------------------------------------------------------------------------------

A board which has an EEPRON issue

3041DS, Sys ID: 0x1c, Sys Ver: 0x11, FPGA Ver: 0x05, vBank: 0
36-bit Addressing

 

U-Boot 2011.12-00030-gad15412 (May 02 2012 - 15:53:05)
CPU0:  P3041E, Version: 1.0, (0x82190310)
Core:  E500MC, Version: 2.2, (0x80230022)
Clock Configuration:
       CPU0:750  MHz, CPU1:750  MHz, CPU2:750  MHz, CPU3:750  MHz,
       CCB:500  MHz,
       DDR:416.667 MHz (833.333 MT/s data rate) (Asynchronous), LBC:62.500 MHz
       FMAN1: 250 MHz
       PME:   250 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: P

Reset Configuration Word (RCW):
       00000000: 4c140000 00000000 12121414 00008888
       00000010: 00000000 00000000 fe800000 01000000
       00000020: 00000000 00000000 00000000 00030000
       00000030: 00000000 00000000 00000000 00000000
SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz
I2C:   ready
SPI:   ready
DRAM:  Initializing....using SPD
Detected UDIMM i-DIMM
2 GiB (DDR3, 64-bit, CL=6, ECC on)
       DDR Chip-Select Interleaving Mode: CS0+CS1
Testing 0x00000000 - 0x7fffffff
Remap DDR
POST memory PASSED
Flash: 128 MiB
L2:    128 KB enabled
Corenet Platform Cache: 1024 KB enabled
SRIO1: disabled
SRIO2: disabled
NAND:  1024 MiB
MMC:  FSL_SDHC: 0
*** Warning - bad CRC, using default environment
EEPROM: Invalid ID (ff ff ff ff)
PCIe1: disabled
PCIe2: disabled
PCIe3: disabled
PCIe4: disabled
In:    serial
Out:   serial
Err:   serial
Warning: SERDES bank 2 expects reference clock 100MHz, but actual is 125MHz
Warning: SERDES bank 3 expects reference clock 100MHz, but actual is 125MHz
Net:   Initializing Fman
Fman1: Data at ef000000 is not a firmware
No ethernet found.
Hit any key to stop autoboot:  0
No ethernet found.
No ethernet found.
WARNING: adjusting available memory to 30000000
Wrong Image Format for bootm command
ERROR: can't get kernel image!
=>

----------------------------------------------------------------------

Another board which functions correctly

 

U-Boot 2011.12-00030-gad15412 (May 02 2012 - 15:53:05)

CPU0: P3041E, Version: 2.0, (0x82190320)
Core: E500MC, Version: 3.2, (0x80230032)
Clock Configuration:
CPU0:1500 MHz, CPU1:1500 MHz, CPU2:1500 MHz, CPU3:1500 MHz,
CCB:750 MHz,
DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:93.750 MHz
FMAN1: 583.333 MHz
PME: 375 MHz
L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Board: P3041DS, Sys ID: 0x1c, Sys Ver: 0x12, FPGA Ver: 0x05, vBank: 0
36-bit Addressing
Reset Configuration Word (RCW):
00000000: 12600000 00000000 241c0000 00000000
00000010: d8804c00 03002000 fe800000 41000000
00000020: 00000000 00000000 00000000 10c30001
00000030: a8000000 00000000 00000000 00000000
SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz
I2C: ready
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM i-DIMM
2 GiB (DDR3, 64-bit, CL=9, ECC on)
DDR Chip-Select Interleaving Mode: CS0+CS1
Testing 0x00000000 - 0x7fffffff
Remap DDR
POST memory PASSED
Flash: 128 MiB
L2: 128 KB enabled
Corenet Platform Cache: 1024 KB enabled
SERDES: timeout resetting bank 3
SRIO1: disabled
SRIO2: disabled
NAND: 1024 MiB
MMC: FSL_SDHC: 0
EEPROM: NXID v1
PCIe1: Root Complex, no link, regs @ 0xfe200000
PCIe1: Bus 00 - 00
PCIe2: disabled
PCIe3: Root Complex, no link, regs @ 0xfe202000
PCIe3: Bus 01 - 01
PCIe4: disabled
In: serial
Out: serial
Err: serial
Warning: SERDES bank 3 expects reference clock 100MHz, but actual is 125MHz
Net: Initializing Fman
Fman1: Uploading microcode version 101.8.0
PHY reset timed out
PHY reset timed out
PHY reset timed out
PHY reset timed out
PHY reset timed out
FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 [PRIME], FM1@TGEC1
Hit any key to stop autoboot: 0
=> printenv
baudrate=115200
bdev=sda3
bootcmd=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;bootm e8020000 e9300000 e8800000
bootdelay=3
bootfile=bootApp_p3041.bin
consoledev=ttyS0
eth1addr=00:04:9F:00:5A:19
eth2addr=00:04:9F:00:5A:1A
eth3addr=00:04:9F:00:5A:1B
eth4addr=00:04:9F:00:5A:1C
eth5addr=00:04:9F:00:5A:1D
ethact=FM1@DTSEC5
ethaddr=00:04:9F:00:5A:18
ethprime=FM1@DTSEC5
fdtaddr=c00000
fdtfile=p5020ds.dtb
fman_ucode=0xef000000
gatewayip=192.168.178.1
hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;fsl_fm1_xaui_phy:xfi
ipaddr=192.168.178.65
loadaddr=1000000
netdev=eth0
netmask=255.255.255.0
nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr
ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;tftp $ramdiskaddr $ramdiskfile;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr $ramdiskaddr $fdtaddr
ramdiskaddr=2000000
ramdiskfile=rootfs.ext2.gz.uboot
rootpath=/opt/nfsroot
serverip=192.168.178.63
stderr=serial
stdin=serial
stdout=serial
tftpflash=tftpboot $loadaddr $uboot && protect off $ubootaddr +$filesize && erase $ubootaddr +$filesize && cp.b $loadaddr $ubootaddr $filesize && protect on $ubootaddr +$filesize && cmp.b $loadaddr $ubootaddr $filesize
uboot=u-boot.bin
ubootaddr=0xeff80000

Environment size: 1549/8188 bytes

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20 Replies

538 Views
Contributor I

Already, all dip switches and jumpers were matched with the working version.

Attached are 2 photos taken of the faulty board.

First photo taken is the  complete board.

Second photo is a section of the board that was reworked.

Another note to keep in mind, the board has a sticker which is labelled as  "S/N prototype 0073"

In my opinion, It could be that the board was an earlier version therefore some rework was done  on the board.

Attention New information:-You mention that you wanted good quality photos! Each photo is 3MBytes each but a message pops up that I've exceeded the  max memory that I'm allowed to send! How do I send these photos then!! Can I send them via your email ufedor? Please provide me a means to send them to you. 

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NXP TechSupport
NXP TechSupport

Try to send the photos in separate responses.

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510 Views
Contributor I

Unfortunately, with one photo I have exceeded the 3MB nxp web limit (my photo is actually 3436KB!)

 

 

 

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499 Views
Contributor I

Can I send the photos via NXP email then?

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497 Views
Contributor I

This is the message I get when I attach one photo:

sidiropoulos_ch_0-1600171246922.png

 

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488 Views
NXP TechSupport
NXP TechSupport

Please put the images to any cloud drive and send a link.

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483 Views
Contributor I
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476 Views
NXP TechSupport
NXP TechSupport

Please try to execute "mac" command in U-Boot and provide the result.

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Contributor I

Below is the MAC command. I believe the results is a  consequence to the EEPROM data being corrupted:

U-Boot 2011.12-00030-gad15412 (May 02 2012 - 15:53:05)

CPU0: P3041E, Version: 1.1, (0x82190311)
Core: E500MC, Version: 2.2, (0x80230022)
Clock Configuration:
CPU0:750 MHz, CPU1:750 MHz, CPU2:750 MHz, CPU3:750 MHz,
CCB:500 MHz,
DDR:416.667 MHz (833.333 MT/s data rate) (Asynchronous), LBC:62.500 MHz
FMAN1: 250 MHz
PME: 250 MHz
L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Board: P3041DS, Sys ID: 0x1c, Sys Ver: 0x11, FPGA Ver: 0x05, vBank: 0
36-bit Addressing
Reset Configuration Word (RCW):
00000000: 4c140000 00000000 12121414 00008888
00000010: 00000000 00000000 fe800000 01000000
00000020: 00000000 00000000 00000000 00030000
00000030: 00000000 00000000 00000000 00000000
SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz
I2C: ready
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM i-DIMM
2 GiB (DDR3, 64-bit, CL=6, ECC on)
DDR Chip-Select Interleaving Mode: CS0+CS1
Testing 0x00000000 - 0x7fffffff
Remap DDR
POST memory PASSED
Flash: 128 MiB
L2: 128 KB enabled
Corenet Platform Cache: 1024 KB enabled
SRIO1: disabled
SRIO2: disabled
NAND: 1024 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment

EEPROM: Invalid ID (ff ff ff ff)
PCIe1: disabled
PCIe2: disabled
PCIe3: disabled
PCIe4: disabled
In: serial
Out: serial
Err: serial
Warning: SERDES bank 2 expects reference clock 100MHz, but actual is 125MHz
Warning: SERDES bank 3 expects reference clock 100MHz, but actual is 125MHz
Net: Initializing Fman
Fman1: Data at ef000000 is not a firmware
No ethernet found.
Hit any key to stop autoboot: 0
=> mac
ID: ---- v4294967295
SN: ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Errata: ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Build date: 20ff/ff/ff 7f:ff:ff PM
Eth0: ff:ff:ff:ff:ff:ff
Eth1: ff:ff:ff:ff:ff:ff
Eth2: ff:ff:ff:ff:ff:ff
Eth3: ff:ff:ff:ff:ff:ff
Eth4: ff:ff:ff:ff:ff:ff
Eth5: ff:ff:ff:ff:ff:ff
Eth6: ff:ff:ff:ff:ff:ff
Eth7: ff:ff:ff:ff:ff:ff
Eth8: ff:ff:ff:ff:ff:ff
Eth9: ff:ff:ff:ff:ff:ff
Eth10: ff:ff:ff:ff:ff:ff
Eth11: ff:ff:ff:ff:ff:ff
Eth12: ff:ff:ff:ff:ff:ff
Eth13: ff:ff:ff:ff:ff:ff
Eth14: ff:ff:ff:ff:ff:ff
Eth15: ff:ff:ff:ff:ff:ff
Eth16: ff:ff:ff:ff:ff:ff
Eth17: ff:ff:ff:ff:ff:ff
Eth18: ff:ff:ff:ff:ff:ff
Eth19: ff:ff:ff:ff:ff:ff
Eth20: ff:ff:ff:ff:ff:ff
Eth21: ff:ff:ff:ff:ff:ff
Eth22: ff:ff:ff:ff:ff:ff
CRC: ffffffff (should be 5d0c2664)
=>

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NXP TechSupport
NXP TechSupport

Please refer to the attached document.

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438 Views
Contributor I

There was some progress made regarding the EEPROM issue (see listing below in blue).

However, the original problems are still existing (see listing below in red).

for e.g Fman1: Data at ef000000 is not a firmware

should be stated as:- 

Fman1: Uploading microcode version 101.8.0.

 

My question: Is there a possibility that an FPGA need to also be reprogrammed as it was from the factory? If this is the case I'm prepared to send the board and pay for the cost to perform this.

-------------------------------------//-----------------------------------------------------------------

U-Boot 2011.12-00030-gad15412 (May 02 2012 - 15:53:05)

CPU0: P3041E, Version: 1.1, (0x82190311)
Core: E500MC, Version: 2.2, (0x80230022)
Clock Configuration:
CPU0:750 MHz, CPU1:750 MHz, CPU2:750 MHz, CPU3:750 MHz,
CCB:500 MHz,
DDR:416.667 MHz (833.333 MT/s data rate) (Asynchronous), LBC:62.500 MHz
FMAN1: 250 MHz
PME: 250 MHz
L1: D-cache 32 kB enabled
I-cache 32 kB enabled
Board: P3041DS, Sys ID: 0x1c, Sys Ver: 0x11, FPGA Ver: 0x05, vBank: 0
36-bit Addressing
Reset Configuration Word (RCW):
00000000: 4c140000 00000000 12121414 00008888
00000010: 00000000 00000000 fe800000 01000000
00000020: 00000000 00000000 00000000 00030000
00000030: 00000000 00000000 00000000 00000000
SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz
I2C: ready
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM i-DIMM
2 GiB (DDR3, 64-bit, CL=6, ECC on)
DDR Chip-Select Interleaving Mode: CS0+CS1
Testing 0x00000000 - 0x7fffffff
Remap DDR
POST memory PASSED
Flash: 128 MiB
L2: 128 KB enabled
Corenet Platform Cache: 1024 KB enabled
SRIO1: disabled
SRIO2: disabled
NAND: 1024 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment

EEPROM: NXID v1
PCIe1: disabled
PCIe2: disabled
PCIe3: disabled
PCIe4: disabled
In: serial
Out: serial
Err: serial
Warning: SERDES bank 2 expects reference clock 100MHz, but actual is 125MHz
Warning: SERDES bank 3 expects reference clock 100MHz, but actual is 125MHz
Net: Initializing Fman
Fman1: Data at ef000000 is not a firmware
No ethernet found.
Hit any key to stop autoboot: 0
No ethernet found.
No ethernet found.
WARNING: adjusting available memory to 30000000
Wrong Image Format for bootm command
ERROR: can't get kernel image!
=> mac
ID: NXID v1
SN: 123456
Errata: 1.0
Build date: 2020/09/16 16:45:04
Eth0: 00:04:9f:00:fe:69
Eth1: 00:04:9f:00:fe:6a
Eth2: 00:04:9f:00:fe:6b
Eth3: 00:04:9f:00:fe:6c
Eth4: 00:04:9f:00:fe:6d
Eth5: 00:04:9f:00:fe:6e
CRC: 95ac15a9
=>

--------------------------------------//--------------------------------------------------

 

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NXP TechSupport
NXP TechSupport

FMan firmware was erased on the problem board.

Most convenient way is to use CodeWarrior Flash Programmer and re-program complete NOR Flash image provided in the QorIQ Linux SDK v2.0 PPCE500MC IMAGE.iso which is available for download here:

https://www.nxp.com/design/software/embedded-software/linux-software-and-development-tools/linux-sdk...

 

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Contributor I

Hi Ufeder,

Sorry for not getting back to you earlier.... I have updated the UBOOT with the iso image that you mentioned and the results look a lot better! The frequency CPU clock also went from 750MHz to 1500MHZ clock speed. of course I had to redo mac address settings due to the new UBOOT version.

Below is what I have configured in CW for flashing the new UBOOT image(*.bin) version.

Basically I launched CW as a BareBoard. But was only interested in the connectivity between my board and CW Tap and then created a target task (as shown below) start (Current NOR Address)E8000000 to EFFFFFFF with an  offset of E8000000.  The connectivity is important  as it initialises the board with the corresponding BSP(tcl)

In fact the loading of the image stopped loading at around  EFF00000 instead of EFFFFFFF. It maybe that the rest of the image contains "FFFFFF..FFFF".

 

However, in the Boot listing below I'm getting:-

Could not get PHY for HYDRA_SGMII_MDIO: addr 28
Failed to connect
Could not get PHY for HYDRA_SGMII_MDIO: addr 29
Failed to connect
Could not get PHY for HYDRA_SGMII_MDIO: addr 30
Failed to connect
Could not get PHY for HYDRA_RGMII_MDIO: addr 0
Failed to connect
Could not get PHY for HYDRA_RGMII_MDIO: addr 1
Failed to connect
Could not get PHY for FM_TGEC_MDIO: addr 0
Failed to connect

Is this a problem which I can ignore?

 

Thanks

CW_Flash_NOR_Programmer.JPG

--------------------------------------------------//-----------------------------------------------------------------

Programming passed.
=> mac
ID: NXID v1
SN: 654321
Errata: 1
Build date: 2020/09/13 21:10:10
Eth0: 00:04:9f:00:fe:69
Eth1: 00:04:9f:00:fe:6a
Eth2: 00:04:9f:00:fe:6b
Eth3: 00:04:9f:00:fe:6c
Eth4: 00:04:9f:00:fe:6d
Eth5: 00:04:9f:00:fe:6e
CRC: 9b8e9912
=>

U-Boot 2016.012.0+ga9b437f (May 15 2016 - 03:40:53 +0800)

CPU0: P3041E, Version: 1.1, (0x82190311)
Core: e500mc, Version: 2.2, (0x80230022)
Clock Configuration:
CPU0:1500 MHz, CPU1:1500 MHz, CPU2:1500 MHz, CPU3:1500 MHz,
CCB:750 MHz,
DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:93.750 MHz
FMAN1: 583.333 MHz
QMAN: 375 MHz
PME: 375 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 12600000 00000000 241c0000 00000000
00000010: d8984a01 03002000 de800000 41000000
00000020: 00000000 00000000 00000000 10070000
00000030: 00000000 00000000 00000000 00000000
I2C: ready
Board: P3041DS, Sys ID: 0x1c, Sys Ver: 0x11, FPGA Ver: 0x05, vBank: 0
SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM i-DIMM
Testing 0x00000000 - 0x7fffffff
Remap DDR
2 GiB (DDR3, 64-bit, CL=9, ECC on)
DDR Chip-Select Interleaving Mode: CS0+CS1
POST memory PASSED
Flash: 128 MiB
L2: 128 KiB enabled
Corenet Platform Cache: 1 MiB enabled
SRIO1: disabled
SRIO2: disabled
NAND: 1024 MiB
MMC: FSL_SDHC: 0
EEPROM: NXID v1
PCIe1: Root Complex, no link, regs @ 0xfe200000
PCIe1: Bus 00 - 00
PCIe2: disabled
PCIe3: Root Complex, no link, regs @ 0xfe202000
PCIe3: Bus 01 - 01
PCIe4: disabled
In: serial
Out: serial
Err: serial
Net: Initializing Fman
Fman1: Uploading microcode version 106.1.18
Could not get PHY for HYDRA_SGMII_MDIO: addr 28
Failed to connect
Could not get PHY for HYDRA_SGMII_MDIO: addr 29
Failed to connect
Could not get PHY for HYDRA_SGMII_MDIO: addr 30
Failed to connect
Could not get PHY for HYDRA_RGMII_MDIO: addr 0
Failed to connect
Could not get PHY for HYDRA_RGMII_MDIO: addr 1
Failed to connect
Could not get PHY for FM_TGEC_MDIO: addr 0
Failed to connect
FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 [PRIME], FM1@TGEC1
Hit any key to stop autoboot: 0
WARNING: adjusting available memory to 30000000
## Booting kernel from Legacy Image at e8020000 ...
Image Name: Linux-4.1.8-rt8+gbd51baf
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 4616252 Bytes = 4.4 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at e9300000 ...
Image Name: fsl-image-mfgtool-p3041ds-201605
Image Type: PowerPC Linux RAMDisk Image (gzip compressed)
Data Size: 8388837 Bytes = 8 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
## Flattened Device Tree blob at e8800000
Booting using the fdt blob at 0xe8800000
Uncompressing Kernel Image ... OK
Loading Ramdisk to 2f7ff000, end 2ffff0e5 ... OK
Loading Device Tree to 03fe4000, end 03fff8f9 ... OK
Reserved memory: initialized node bman-fbpr, compatible id fsl,bman-fbpr
Reserved memory: initialized node qman-fqd, compatible id fsl,qman-fqd
Reserved memory: initialized node qman-pfdr, compatible id fsl,qman-pfdr
Using CoreNet Generic machine description
Memory CAM mapping: 256/256/256 Mb, residual: 1280Mb
Linux version 4.1.8-rt8+gbd51baf (jenkins@mercury) (gcc version 4.9.2 (GCC) ) #1 SMP Sun May 15 03:41:49 CST 2016
Found initrd at 0xef7ff000:0xeffff0e5
CPU maps initialized for 1 thread per core
bootconsole [udbg0] enabled
setup_arch: initmem
CoreNet Generic board
arch: exit
Zone ranges:
DMA [mem 0x0000000000000000-0x000000002fffffff]
Normal empty
HighMem [mem 0x0000000030000000-0x000000007fffffff]
Movable zone start for each node
Early memory node ranges
node 0: [mem 0x0000000000000000-0x000000007fffffff]
Initmem setup node 0 [mem 0x0000000000000000-0x000000007fffffff]
MMU: Allocated 1088 bytes of context maps for 255 contexts
PERCPU: Embedded 12 pages/cpu @ee77d000 s19148 r8192 d21812 u49152
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 522752
Kernel command line: root=/dev/ram rw console=ttyS0,115200
log_buf_len individual max cpu contribution: 4096 bytes
log_buf_len total cpu_extra contributions: 12288 bytes
log_buf_len min size: 16384 bytes
log_buf_len: 32768 bytes
early log buf free: 13464(82%)
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Sorting __ex_table...
Memory: 1937588K/2097152K available (7172K kernel code, 308K rwdata, 2020K rodata, 308K init, 458K bss, 159564K reserved, 0K cma-reserved, 1253368K highmem)
Kernel virtual memory layout:
* 0xfff5f000..0xfffff000 : fixmap
* 0xffc00000..0xffe00000 : highmem PTEs
* 0xffbfd000..0xffc00000 : early ioremap
* 0xf1000000..0xffbfd000 : vmalloc & ioremap
Hierarchical RCU implementation.
RCU debugfs-based tracing is enabled.
Additional per-CPU info printed with stalls.
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
NR_IRQS:512 nr_irqs:512 16
mpic: Setting up MPIC " OpenPIC " version 1.2 at ffe040000, max 4 CPUs
mpic: ISU size: 512, shift: 9, mask: 1ff
mpic: Initializing for 512 sources
clocksource timebase: mask: 0xffffffffffffffff max_cycles: 0x567c8a606, max_idle_ns: 440795202272 ns
clocksource: timebase mult[2aaaaaab] shift[24] registered
Console: colour dummy device 80x25
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
e500 family performance monitor hardware support registered
Brought up 4 CPUs
devtmpfs: initialized
clocksource jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
NET: Registered protocol family 16
Bman ver:0a02,01,00
qman-fqd addr 0x7f000000 size 0x800000
qman-pfdr addr 0x7c000000 size 0x2000000
Qman ver:0a01,01,02,00

Found FSL PCI host bridge at 0x0000000ffe200000. Firmware bus number: 0->0
PCI host bridge /pcie@ffe200000 ranges:
MEM 0x0000000c00000000..0x0000000c1fffffff -> 0x00000000e0000000
IO 0x0000000ff8000000..0x0000000ff800ffff -> 0x0000000000000000
/pcie@ffe200000: PCICSRBAR @ 0xdf000000
setup_pci_atmu: end of DRAM 80000000
EDAC PCI0: Giving out device to module MPC85xx_edac controller mpc85xx_pci_err: DEV ffe200000.pcie (INTERRUPT)
MPC85xx_edac acquired irq 482 for PCI Err
MPC85xx_edac PCI err registered
Found FSL PCI host bridge at 0x0000000ffe202000. Firmware bus number: 0->0
PCI host bridge /pcie@ffe202000 ranges:
MEM 0x0000000c40000000..0x0000000c5fffffff -> 0x00000000e0000000
IO 0x0000000ff8020000..0x0000000ff802ffff -> 0x0000000000000000
/pcie@ffe202000: PCICSRBAR @ 0xdf000000
setup_pci_atmu: end of DRAM 80000000
EDAC PCI1: Giving out device to module MPC85xx_edac controller mpc85xx_pci_err: DEV ffe202000.pcie (INTERRUPT)
MPC85xx_edac acquired irq 480 for PCI Err
MPC85xx_edac PCI err registered
PCI: Probing PCI hardware
fsl-pci ffe200000.pcie: PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [io 0xf1040000-0xf104ffff] (bus address [0x0000-0xffff])
pci_bus 0000:00: root bus resource [mem 0xc00000000-0xc1fffffff] (bus address [0xe0000000-0xffffffff])
pci_bus 0000:00: root bus resource [bus 00-ff]
pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
pci 0000:00:00.0: PCI bridge to [bus 01-ff]
fsl-pci ffe202000.pcie: PCI host bridge to bus 0001:02
pci_bus 0001:02: root bus resource [io 0xf1060000-0xf106ffff] (bus address [0x0000-0xffff])
pci_bus 0001:02: root bus resource [mem 0xc40000000-0xc5fffffff] (bus address [0xe0000000-0xffffffff])
pci_bus 0001:02: root bus resource [bus 02-ff]
pci 0001:02:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
pci 0001:02:00.0: PCI bridge to [bus 03-ff]
PCI: Cannot allocate resource region 0 of device 0000:00:00.0, will remap
PCI: Cannot allocate resource region 0 of device 0001:02:00.0, will remap
pci 0000:00:00.0: BAR 0: no space for [mem size 0x01000000]
pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x01000000]
pci 0000:00:00.0: PCI bridge to [bus 01]
pci 0000:00:00.0: bridge window [io 0xf1040000-0xf104ffff]
pci 0000:00:00.0: bridge window [mem 0xc00000000-0xc1fffffff]
pci_bus 0000:00: Some PCI device resources are unassigned, try booting with pci=realloc
pci 0001:02:00.0: BAR 0: no space for [mem size 0x01000000]
pci 0001:02:00.0: BAR 0: failed to assign [mem size 0x01000000]
pci 0001:02:00.0: PCI bridge to [bus 03]
pci 0001:02:00.0: bridge window [io 0xf1060000-0xf106ffff]
pci 0001:02:00.0: bridge window [mem 0xc40000000-0xc5fffffff]
pci_bus 0001:02: Some PCI device resources are unassigned, try booting with pci=realloc
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
bman-fbpr addr 0x7e000000 size 0x1000000
Bman err interrupt handler present
Bman portal initialised, cpu 0
Bman portal initialised, cpu 1
Bman portal initialised, cpu 2
Bman portal initialised, cpu 3
Bman portals initialised
Qman err interrupt handler present
Qman portal initialised, cpu 0
Qman portal initialised, cpu 1
Qman portal initialised, cpu 2
Qman portal initialised, cpu 3
Qman portals initialised
Bman: BPID allocator includes range 32:32
Qman: FQID allocator includes range 256:256
Qman: FQID allocator includes range 32768:32768
Qman: CGRID allocator includes range 0:256
Qman: pool channel allocator includes range 33:15
No USDPAA memory, no 'fsl,usdpaa-mem' in device-tree
Switched to clocksource timebase
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Trying to unpack rootfs image as initramfs...
rootfs image is not initramfs (no cpio magic); looks like an initrd
Freeing initrd memory: 8192K (ef7ff000 - effff000)
futex hash table entries: 1024 (order: 4, 65536 bytes)
audit: initializing netlink subsys (disabled)
audit: type=2000 audit(0.512:1): initialized
HugeTLB registered 4 MB page size, pre-allocated 0 pages
HugeTLB registered 16 MB page size, pre-allocated 0 pages
HugeTLB registered 64 MB page size, pre-allocated 0 pages
HugeTLB registered 256 MB page size, pre-allocated 0 pages
HugeTLB registered 1 GB page size, pre-allocated 0 pages
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
ntfs: driver 2.1.32 [Flags: R/O].
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
bounce: pool size: 64 pages
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
pcieport 0000:00:00.0: Signaling PME through PCIe PME interrupt
pcieport 0001:02:00.0: Signaling PME through PCIe PME interrupt
Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
console [ttyS0] disabled
serial8250.0: ttyS0 at MMIO 0xffe11c500 (irq = 36, base_baud = 23437499) is a 16550A
console [ttyS0] enabled
console [ttyS0] enabled
bootconsole [udbg0] disabled
bootconsole [udbg0] disabled
serial8250.0: ttyS1 at MMIO 0xffe11c600 (irq = 36, base_baud = 23437499) is a 16550A
serial8250.0: ttyS2 at MMIO 0xffe11d500 (irq = 37, base_baud = 23437499) is a 16550A
serial8250.0: ttyS3 at MMIO 0xffe11d600 (irq = 37, base_baud = 23437499) is a 16550A
ePAPR hypervisor byte channel driver
Generic non-volatile memory driver v1.1
brd: module loaded
loop: module loaded
st: Version 20101219, fixed bufsize 32768, s/g segs 256
fsl-sata ffe220000.sata: Sata FSL Platform/CSB Driver init
scsi host0: sata_fsl
ata1: SATA max UDMA/133 irq 68
fsl-sata ffe221000.sata: Sata FSL Platform/CSB Driver init
scsi host1: sata_fsl
ata2: SATA max UDMA/133 irq 69
fe8000000.flash: Found 1 x16 devices at 0x0 in 16-bit bank. Manufacturer ID 0x000001 Chip ID 0x002801
Amd/Fujitsu Extended Query Table at 0x0040
Amd/Fujitsu Extended Query version 1.3.
number of CFI chips: 1
nand: device found, Manufacturer ID: 0x20, Chip ID: 0xd3
nand: ST Micro NAND08GW3B2CN6
nand: 1024 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
Bad block table found at page 524224, version 0x01
Bad block table found at page 524160, version 0x01
nand_read_bbt: bad block at 0x00001c180000
6 ofpart partitions found on MTD device fffa00000.flash
Creating 6 MTD partitions on "fffa00000.flash":
0x000000000000-0x000002000000 : "NAND U-Boot Image"
0x000002000000-0x000012000000 : "NAND Root File System"
0x000012000000-0x00001a000000 : "NAND Compressed RFS Image"
0x00001a000000-0x00001e000000 : "NAND Linux Kernel Image"
0x00001e000000-0x00001f000000 : "NAND DTB Image"
0x00001f000000-0x000040000000 : "NAND Writable User area"
eLBC NAND device at 0xfffa00000, bank 2
fsl_espi ffe110000.spi: cs=0, init_csmode=0x100008
m25p80 spi32766.0: found s25fl129p1, expected s25sl12801
m25p80 spi32766.0: s25fl129p1 (16384 Kbytes)
fsl_espi ffe110000.spi: at 0xf1a2e000 (irq = 53)
libphy: Fixed MDIO Bus: probed
mdio-mux-mmioreg fffdf0009.mdio-mux-emi1: failed to register mdio-mux bus /localbus@ffe124000/board-control@3,0/mdio-mux-emi1
libphy: Freescale PowerQUICC MII Bus: probed
libphy: Freescale XGMAC MDIO Bus: probed
mdio_bus ffe4f1000: Error while reading PHY4 reg at 1.6
mdio_bus ffe4f1000: Error while reading PHY4 reg at 1.5
mdio_bus ffe4f1000: Error while reading PHY4 reg at 0.6
mdio_bus ffe4f1000: Error while reading PHY4 reg at 0.5
mdio_bus ffe4f1000: Error while reading PHY0 reg at 1.6
mdio_bus ffe4f1000: Error while reading PHY0 reg at 1.5
mdio_bus ffe4f1000: Error while reading PHY0 reg at 0.6
mdio_bus ffe4f1000: Error while reading PHY0 reg at 0.5
Freescale FM module, FMD API version 21.1.0
Freescale FM Ports module
fsl_mac: fsl_mac: FSL FMan MAC API based driver
fsl_mac ffe4e0000.ethernet: FMan dTSEC version: 0x08240101
fsl_mac ffe4e0000.ethernet: FMan MAC address: 00:04:9f:02:00:dd
fsl_mac ffe4e2000.ethernet: FMan dTSEC version: 0x08240101
fsl_mac ffe4e2000.ethernet: FMan MAC address: 00:04:9f:02:01:dd
fsl_mac ffe4e4000.ethernet: FMan dTSEC version: 0x08240101
fsl_mac ffe4e4000.ethernet: FMan MAC address: 00:04:9f:02:02:dd
fsl_mac ffe4e6000.ethernet: FMan dTSEC version: 0x08240101
fsl_mac ffe4e6000.ethernet: FMan MAC address: 00:04:9f:02:03:dd
fsl_mac ffe4e8000.ethernet: FMan dTSEC version: 0x08240101
fsl_mac ffe4e8000.ethernet: FMan MAC address: 00:04:9f:02:04:dd
cpu1/8: Applying 10G TX ECC workaround (10GMAC-A004) ...
cpu1/8: done.
fsl_mac ffe4f0000.ethernet: FMan XGEC version: 0x00010330
fsl_mac ffe4f0000.ethernet: FMan MAC address: 00:04:9f:02:05:dd
fsl_dpa: FSL DPAA Ethernet driver
fsl_dpa: fsl_dpa: Probed interface eth0
fsl_dpa: fsl_dpa: Probed interface eth1
fsl_dpa: fsl_dpa: Probed interface eth2
fsl_dpa: fsl_dpa: Probed interface eth3
fsl_dpa: fsl_dpa: Probed interface eth4
fsl_advanced: FSL DPAA Advanced drivers:
fsl_proxy: FSL DPAA Proxy initialization driver
fsl_dpa_shared: FSL DPAA Shared Ethernet driver
fsl_dpa_macless: FSL DPAA MACless Ethernet driver
fsl_oh: FSL FMan Offline Parsing port driver
e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
e1000: Copyright (c) 1999-2006 Intel Corporation.
e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
ohci-pci: OHCI PCI platform driver
fsl-ehci fsl-ehci.0: Freescale On-Chip EHCI Host Controller
fsl-ehci fsl-ehci.0: new USB bus registered, assigned bus number 1
fsl-ehci fsl-ehci.0: irq 44, io mem 0xffe210000
fsl-ehci fsl-ehci.0: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
usbcore: registered new interface driver usb-storage
i2c /dev entries driver
mpc-i2c ffe118100.i2c: timeout 1000000 us
mpc-i2c ffe119100.i2c: timeout 1000000 us
rtc-ds3232 1-0068: rtc core: registered ds3232 as rtc0
mpc-i2c ffe118000.i2c: timeout 1000000 us
mpc-i2c ffe119000.i2c: timeout 1000000 us
ina2xx 1-0040: power monitor ina220 (Rshunt = 1000 uOhm)
ina2xx 1-0041: power monitor ina220 (Rshunt = 1000 uOhm)
ina2xx 1-0044: power monitor ina220 (Rshunt = 1000 uOhm)
ina2xx 1-0045: power monitor ina220 (Rshunt = 1000 uOhm)
Freescale(R) MPC85xx EDAC driver, (C) 2006 Montavista Software
EDAC MC0: Giving out device to module MPC85xx_edac controller mpc85xx_mc_err: DEV mpc85xx_mc_err (INTERRUPT)
MPC85xx_edac acquired irq 490 for MC
MPC85xx_edac MC err registered
qoriq_cpufreq: Freescale QorIQ CPU frequency scaling driver
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
ata1: No Device OR PHYRDY change,Hstatus = 0xa0000000
ata1: SATA link down (SStatus 0 SControl 300)
ata2: No Device OR PHYRDY change,Hstatus = 0xa0000000
ata2: SATA link down (SStatus 0 SControl 300)
sdhci-pltfm: SDHCI platform and OF driver helper
/soc@ffe000000/sdhc@114000: voltage-ranges unspecified
sdhci-esdhc ffe114000.sdhc: No vmmc regulator found
sdhci-esdhc ffe114000.sdhc: No vqmmc regulator found
mmc0: SDHCI controller on ffe114000.sdhc [ffe114000.sdhc] using ADMA
platform caam_qi.0: Linux CAAM Queue I/F driver initialised
caam ffe300000.crypto: device ID = 0x0a12010000000000 (Era 3)
caam ffe300000.crypto: job rings = 4, qi = 1
caam algorithms registered in /proc/crypto
platform caam_qi.0: fsl,sec-v4.2 algorithms registered in /proc/crypto
caam_jr ffe301000.jr: registering rng-caam
caam ffe300000.crypto: fsl,sec-v4.2 algorithms registered in /proc/crypto
Freescale USDPAA process driver
fsl-usdpaa: no region found
Freescale USDPAA process IRQ driver
Freescale pme2 db driver
PME2: fsl_pme2_db_init: not on ctrl-plane
Freescale pme2 scan driver
fsl-pme2-scan: device pme_scan registered
Freescale hypervisor management driver
fsl-hv: no hypervisor found
ipip: IPv4 over IPv4 tunneling driver
Initializing XFRM netlink socket
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
Key type dns_resolver registered
libphy: mdio_mux: probed
libphy: mdio_mux: probed
mdio-mux-mmioreg fffdf0009.mdio-mux-emi1: Version 1.0
fsl_generic: FSL DPAA Generic Ethernet driver
rtc-ds3232 1-0068: setting system clock to 2020-08-12 16:52:52 UTC (1597251172)
RAMDISK: gzip image found at block 0
VFS: Mounted root (ext2 filesystem) on device 1:0.
devtmpfs: mounted
Freeing unused kernel memory: 308K (c08fd000 - c094a000)
INIT: version 2.88 booting
Starting udev
udevd[1037]: starting version 182
fsl_dpa fsl,dpaa:ethernet@0 fm1-gb0: renamed from eth0
fsl_dpa fsl,dpaa:ethernet@1 fm1-gb1: renamed from eth1
udevd[1041]: renamed network interface eth0 to fm1-gb0
fsl_dpa fsl,dpaa:ethernet@3 fm1-gb3: renamed from eth2
udevd[1044]: renamed network interface eth1 to fm1-gb1
fsl_dpa fsl,dpaa:ethernet@4 fm1-gb4: renamed from eth3
udevd[1043]: renamed network interface eth2 to fm1-gb3
fsl_dpa fsl,dpaa:ethernet@5 fm1-10g: renamed from eth4
udevd[1045]: renamed network interface eth3 to fm1-gb4
udevd[1046]: renamed network interface eth4 to fm1-10g
bootlogd: cannot allocate pseudo tty: No such file or directory
random: dd urandom read with 2 bits of entropy available
Populating dev cache
Running postinst /etc/rpm-postinsts/100-sysvinit-inittab...
update-rc.d: /etc/init.d/run-postinsts exists during rc.d purge (continuing)
INIT: Entering runlevel: 5up links
Configuring network interfaces... done.
Starting OpenBSD Secure Shell server: sshd
generating ssh RSA key...
generating ssh ECDSA key...
generating ssh DSA key...
generating ssh ED25519 key...
done.
Starting syslogd/klogd: done

QorIQ SDK (FSL Reference Distro) 2.0 p3041ds /dev/ttyS0

p3041ds login:

QorIQ SDK (FSL Reference Distro) 2.0 p3041ds /dev/ttyS0

p3041ds login: random: nonblocking pool is initialized

QorIQ SDK (FSL Reference Distro) 2.0 p3041ds /dev/ttyS0

p3041ds login: root
root@p3041ds:~# cd ..
root@p3041ds:/home# ls
root
root@p3041ds:/home# cd ..
root@p3041ds:/# ls
bin dev home linuxrc media proc sbin tmp var
boot etc lib lost+found mnt run sys usr
root@p3041ds:/#

----------------------------------------------//-----------------------------------------------------------------------------

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Contributor I

Regarding UBoot error list(below), I tried pinging from P3041 to my PC and the connection of the DTSEC4 is Alive! However when I boot from NOR Bank4 (i.e. WIndriver Bootloader resides in NOR BANK4 and comes up OK), P3041 DTSEC4 doesn't communicate with my PC (PC is set as a server) If DTSEC4 was working properly then my PC would load the windriver ELF files  to P3041. But unfortunately the communication times out and windriver bootloader reports can't load/read elf files.

I guess the UBOOT list (below) may indicate that I still have problems with the Ethernet ports!

Can you deduce as to why I am getting such errors!

Thanks

Could not get PHY for HYDRA_SGMII_MDIO: addr 28
Failed to connect
Could not get PHY for HYDRA_SGMII_MDIO: addr 29
Failed to connect
Could not get PHY for HYDRA_SGMII_MDIO: addr 30
Failed to connect
Could not get PHY for HYDRA_RGMII_MDIO: addr 0
Failed to connect
Could not get PHY for HYDRA_RGMII_MDIO: addr 1
Failed to connect
Could not get PHY for FM_TGEC_MDIO: addr 0
Failed to connect

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Contributor I

Could not get PHY for HYDRA_SGMII_MDIO: addr 28

 

Hi Ufedor

Fman microcode version 101.8.0 is what is used on the working board.

Therefore is it possible to give me link of an older image of Fman to try out.

Thank You.

 

Failed to connect
Could not get PHY for HYDRA_SGMII_MDIO: addr 29
Failed to connect
Could not get PHY for HYDRA_SGMII_MDIO: addr 30
Failed to connect
Could not get PHY for HYDRA_RGMII_MDIO: addr 0
Failed to connect
Could not get PHY for HYDRA_RGMII_MDIO: addr 1
Failed to connect
Could not get PHY for FM_TGEC_MDIO: addr 0
Failed to connect

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Contributor I

Ok I will try to load the entire sdk. And hopefully this should restore fman

Thank you for your support

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Contributor I

Great thank you for the info!

I’ll try it and let you know soon.

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NXP TechSupport
NXP TechSupport

Check that all on-board configuration switches are set identically.

In case of further questions please provide a clear photo of the board.

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334 Views
Contributor I

Hi

Is it possible to find me a link of the old original U-boot version which came with my board:-

U-Boot 2011.12-00030-gad15412 (May 02 2012 - 15:53:05)

Maybe with this I can solve the problem with the ethernet connection problem.

 

 

 

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NXP TechSupport
NXP TechSupport

Please check the "PPCE500MC IMAGE.iso" from SDKs previous to V2.0 using the link:

https://www.nxp.com/design/software/embedded-software/linux-software-and-development-tools/linux-sdk...

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