P2020 L2 cache seems to slow down execution

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P2020 L2 cache seems to slow down execution

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alexy_torres-au
Contributor I

Hello,

I have been investigating a CPU stall issue with my project. I realized that the number of instruction completed in a second (number retreived thanks to PMCs) is higher when I disable the L2 cache. 

My tests only uses one core and the second core is disabled.

When L2 cache is disabled, I get 1.25x more instruction completed in a second. The CPI is still low (more than 2) but is better than with L2 enabled.

Can this issue be related to clock settings? If not do you have any idea to investigte the issue?

EDIT: I would like to add that my CPI is between 10 and 20m which is terrible. I think is is linked to this issue, but maybe there is an underlying cause.

Best regards,

Alexy

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Bulat
NXP TechSupport
NXP TechSupport

We nowhere considered the L2 cache as a core's accelerator in the P2020. When enabled, it inserts additional latency to core's transactions due to time required for cache hit checking. If no hit, the transaction is sent to coherent bus, for example to DDR. L2 cache can help to speed up core's operations only if the data being read is absent in the L1 cache but valid in L2 one. This depends on the code and may or may not happen.
Main features of the L2 cache are as follows:
- allows access to the cache for the I/O masters (feature called 'stashing'), in this case the core reads data from the L2 cache instead of DDR;
- allows to share data between two cores.

Regards,

Bulat

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Bulat
NXP TechSupport
NXP TechSupport

We nowhere considered the L2 cache as a core's accelerator in the P2020. When enabled, it inserts additional latency to core's transactions due to time required for cache hit checking. If no hit, the transaction is sent to coherent bus, for example to DDR. L2 cache can help to speed up core's operations only if the data being read is absent in the L1 cache but valid in L2 one. This depends on the code and may or may not happen.
Main features of the L2 cache are as follows:
- allows access to the cache for the I/O masters (feature called 'stashing'), in this case the core reads data from the L2 cache instead of DDR;
- allows to share data between two cores.

Regards,

Bulat

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alexy_torres-au
Contributor I

Hello Bulat,

Thanks for the reply. Is there a possibility to allow a greater hit rate in the L2 cache by enabling the write allocate policy? I did not find any info in the documentation.

Thanks,
Alexy

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Bulat
NXP TechSupport
NXP TechSupport

We consider the P2020 as a processor for networking/telecommunication applications. As I wrote one of the main features is the cache stashing. Allocation can be used by I/O masters (Ethernet, SRIO, PCIe,..) as write policy. This helps a lot because buffer descriptors would be placed into L2, accelerating the core to manage serial traffic between I/O ports.

Regards,

Bulat