P2020 Change Nor Flash From 16M to 32M

[zhaopingyang_sg]

Hi，

 From the BSP P2020_RDB， the Nor Flash size is 16M,from 0xff00_0000 to 0xffff_ffff,but Now i want change the nor flash size to 32M, From 0xfe00_0000 to 0xffff_ffff.

（FLASH_BOOT_ADRS = 0xff00_0000,FLASH_BASE_ADRS = 0xfe00_0000）

follow is my TLB setting：
addis r4, 0, 0x1000 /* TLB1 entry#0 */
ori r4, r4, 0x0000
mtspr MAS0, r4
addis r5, 0, HI(MMU_STATE_VALID|MMU_STATE_IPROT)
ori r5, r5, _MMU_TLB_SZ_16M /* TS = 0, TSIZE = 16 MByte */
mtspr MAS1, r5
addis r6, 0, HI(FLASH_BOOT_ADRS) /* EPN */
ori r6, r6, MMU_ROM_ACCESS
mtspr MAS2, r6
addis r7, 0, HI(FLASH_BOOT_ADRS) /* RPN */
ori r7, r7, 0x0015 /* Supervisor XWR */
mtspr MAS3, r7
tlbwe
tlbsync

addis r4, 0, 0x1001 /* TLB1 entry#0 */
ori r4, r4, 0x0000
mtspr MAS0, r4
addis r5, 0, HI(MMU_STATE_VALID|MMU_STATE_IPROT)
ori r5, r5, _MMU_TLB_SZ_16M /* TS = 0, TSIZE = 16 MByte */
mtspr MAS1, r5
addis r6, 0, HI(FLASH_BASE_ADRS) /* EPN */
ori r6, r6, MMU_ROM_ACCESS
mtspr MAS2, r6
addis r7, 0, HI(FLASH_BASE_ADRS) /* RPN */
ori r7, r7, 0x0015 /* Supervisor XWR */
mtspr MAS3, r7
tlbwe
tlbsync

/*LAW config from 0xfe00_0000 64M size*/

/* Local access window 0 (Nor Flash) initialize */
WRITEADR(r6, r7, M85XX_LAWBAR0(CCSBAR), 0x000fc000)
WRITEADR(r6, r7, M85XX_LAWAR0(CCSBAR), 0x80400019)

/*ELBC Cs 0*/

WRITEADR(r6, r7, M85XX_BR0(CCSBAR), 0xfe001001)
WRITEADR(r6, r7, M85XX_OR0(CCSBAR), 0xfe000030)

but P2020 NorFlash didnot work correct。

I want to know how to config TLB/LAW And eLbc OR and AR register

[zhaopingyang_sg · Accepted solution]

thanks for your answer.

from the doc:

SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,

          MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,

-         0, 2, BOOKE_PAGESZ_64M, 1),

#define CONFIG_FLASH_OR_PRELIM  0xfc000ff7

did it means if i want to use 32M flash,  I need config tlb to 64M？

[ufedor]

> did it means if i want to use 32M flash,  I need config tlb to 64M？

This is very good question.

The simple answer is "yes", but, additionally, you need to correcly specify the TLB Base Address because in the Power Architecture it must be aligned to the window size.

So in case of 32MB NOR Flash you need to configure:

- base address (CONFIG_SYS_FLASH_BASE) and TLB size for 64MB

- Flash size (CONFIG_SYS_MAX_FLASH_SECT) and LAW for 32MB

[ufedor]

Please refer to the attached example file showing all the U-Boot header files modifications required to change the NOR Flash size.