P1010 and AN2919

[fabricedecrop]

Regarding §10.4.2 of P1010 QorIQ Integrated Processor Reference Manual on page 453, I dod not understand FDR value. Does it assume a specific value for DFSRR ?

Because table 6 of AN2919 seems to have the same value of FDR register, but with DFSRR=0x10. Is it correct ?

In P1010 refernce manual, why DFSRR value is no specified for FDR table value ?

Thanks,

Fabrice DECROP

[r8070z]

Have a great day,

Right before the I2Cx_I2CFDR field descriptions the P1010 reference manual says: Refer to application note AN2919, "Determining the I2C Frequency Divider Ratio for SCL", for additional guidance regarding the proper use of I2CFDR and I2CDFSRR.

Value in the I2Cx_I2CFDR field descriptions corresponds to the Table 6 in the Application note because reset value of the I2CDFSRR register is 0x10. They should write that, but unfortunately they did not.

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