On Pci Data missing

[utkarsh_100]

Hi All 

I have T1042 processor on PCIe interface with kintex 7 fpga board . I have test application where data communication b/w Processor & fpga we will be continuously . But moment Processor reads data from fpga it was observed data is getting missed . I meant if processor  expecting data for example 1,2,3,4,5 & soon , it will get like 1 ,8,9,15,22, & soon . 

On processor side I have checked AER register  & other also but could not find error on register level . Please find Log for processor & fpga below

PROCESSOR INFORMATION 

vendor ID = 0x1957
device ID = 0x0825
command register = 0x0007
status register = 0x0010
revision ID = 0x11
class code = 0x0b
sub class code = 0x20
programming interface = 0x00
cache line = 0x10
latency time = 0x00
header type = 0x01
BIST = 0x00
base address 0 = 0x00000000
base address 1 = 0x00000000
primary bus number = 0x00
secondary bus number = 0x01
subordinate bus number = 0x01
secondary latency timer = 0x00
IO base = 0xf1
IO limit = 0x01
secondary status = 0x0000
memory base = 0xa000
memory limit = 0xa030
prefetch memory base = 0xfff1
prefetch memory limit = 0x0001
prefetch memory base upper = 0x00000000
prefetch memory limit upper = 0x00000000
IO base upper 16 bits = 0xffff
IO limit upper 16 bits = 0x000f
expansion ROM base address = 0x00000000
interrupt line = 0x00
interrupt pin = 0x00
bridge control = 0x0000
Capabilities - Power Management
Capabilities - PCIe: Root Port, IRQ 0
Device: Max Payload: 256 bytes, Extended Tag: 5-bit
Acceptable Latency: L0 - <64ns, L1 - <1us
Errors Enabled: Non-Fatal Fatal Unsupported RequestRelaxed Ordering No Snoop

Max Read Request 512 bytes
Link: MAX Speed - 5.0Gb/s, MAX Width - by 4 Port - 0 ASPM - L0s
Latency: L0s - <2us, L1 - >64us
ASPM - Disabled, RCB - 128bytes
Speed - 5.0Gb/s, Width - by 2
Root Control Enabled:
Ext Capabilities - Advanced Error Reporting. 0x100. Version 1. AER Control: 0xa0
Uncorrectable : Mask 0x0. Severity 0x62010
Uncorrectable Status: Correctable : Mask 0x2000.
Correctable Status:
HeaderLog:
Error Source Identification: 0x0 0x0

FPGA  INFORMATION

vendor ID = 0x10ee
device ID = 0x7022
command register = 0x0007
status register = 0x0010
revision ID = 0x00
class code = 0x05
sub class code = 0x80
programming interface = 0x00
cache line = 0x10
latency time = 0x00
header type = 0x00
BIST = 0x00
base address 0 = 0xa0000000
base address 1 = 0x00000000
base address 2 = 0x00000000
base address 3 = 0x00000000
base address 4 = 0x00000000
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x10ee
sub system ID = 0x0007
expansion ROM base address = 0x00000000
interrupt line = 0x29
interrupt pin = 0x01
min Grant = 0x00
max Latency = 0x00
Capabilities - Power Management
Capabilities - Message Signaled Interrupts: 0x48 control 0x80 Disabled, 64-bit, MME: 0 MMC: 0
Address: 0000000000000000 Data: 0x0000
Per-vector Mask: Unsupported
Capabilities - PCIe: Endpoint, IRQ 0
Device: Max Payload: 256 bytes, Phantom Funcs 1 msb, Extended Tag: 8-bit
Acceptable Latency: L0 - <64ns, L1 - <1us
Errors Enabled: Relaxed Ordering No Snoop

Max Read Request 512 bytes
Link: MAX Speed - 5.0Gb/s, MAX Width - by 2 Port - 0 ASPM - L0s
Latency: L0s - >4us, L1 - >64us
ASPM - Disabled, RCB - 64bytes
Speed - 5.0Gb/s, Width - by 2
Ext Capabilities - Device Serial Number. 0x100. Version 1
Serial Number: 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Kindly provide solution where I need to look .into 

Thanks 

[ufedor]

Provided problem description is not clear.

What exactly does it mean: "Processor reads data from fpga"?

What is the read transaction data size?

How exactly the read operation is performed by the T1042?

You wrote:

> expecting data for example 1,2,3,4,5

Please provide example memory dump of this structure.

How exactly the data structure is formed in the FPGA?

Can you check that the data is not corrupted at the FPGA side?

Ensure that the T1042 PCIe Outbound Window is configured as cache-inhibited in the MMU.

[utkarsh_100]

>>>> What exactly does it mean: "Processor reads data from fpga"?

            Fpga will be continuously writing onto the processor .Sorry for not explaining properly I meant Data is getting missed from the processor .

FPGA continuously  write data in the series 1,2,3,4,5,6,7,8,9,10,11,12,13,14 & soon, but I guess processor is missing the data .On processor it gets  data like in pattern  1,2,3,5,6,7,9,10,11,13,14,15,17,18,19. Processor missed the data 4,8,12,16 & soon. 

>>>> What is the read transaction data size?

I guess data size is not the issue, It looks like some logical error. 

>>>>How exactly the data structure is formed in the FPGA?

>>>>Can you check that the data is not corrupted at the FPGA side?

Not sure the data structure in the fpga ,as I am looking onto the processor side . Need to check with the fpga team . 

On chip scope we have measure there in no corruption of data on the fpga side

>>>>>Ensure that the T1042 PCIe Outbound Window is configured as cache-inhibited in the MMU.

How to make sure the Outbound window is configured as cache-inhibited

[ufedor]

>  Fpga will be continuously writing onto the processor .Sorry for not explaining properly

Which exactly data transfer is performed.

Please provide detailed explanation from your software/FPGA team.