We check that LGPL [04] / LGTA / LFRB / LUPWAIT has been pulled up, specifically it is pulled up to 3.3V through a 4.7K resistor.
One thing to add is that we actually mount 3 hardware devices on ELBC, CS0 (base address is 0xF0000000) and CS1 (base address is 0xF4000000) each mount 1 piece of NorFlash, the model is the same, the size is 32MB, in CS2 1 FPGA is mounted on it;
The following 2 phenomena were observed today:
First explain the current configuration of ELBC:
efe05000: f0001001 fc000e41 f4001001 fc000e41 .......A.......A
efe05010: ea001001 ffc00e31
[Phenomena 1] Both CS0 and CS1 can read and write 64MB, and the data will be there after power failure. The actual chip should be 32MB;
[Phenomena 2] When CS0 is normal and CS1 is abnormal (here means that the ID cannot be read correctly, the readout is 0xF400), write and read after CS0 is erased, and it is found that the data is normally written to CS0, but the program is read before erasing The original value of CS1;