Next-To-Last byte I2C Concept

[love_hate_and_repeat]

I read T1040 reference manual and encountered the following explanation but i actually didnt understand it.

"for a multiple byte transfer before reading the next-to-last byte in I2CDR, which causes the master receiver to not acknowledge the next transfer and to automatically generate a STOP at the conclusion of the next transfer"

if master-receiver sends NACK for next-to-last-byte  then this means we cannot get last byte from slave transmitter because we send a NACK for last byte that we didnt read it yet.

and by the way, when i set I2CCR[TXAK] , the NACK is sending to slave transmitter for the byte that i read it from I2CDR register ?

can you explain this concept for me ?

[love_hate_and_repeat]

thanks for your explanation. I understood why we need a dummy read for single byte transfer.

[r8070z]

TXAK specifies the value driven by receiver onto the SDA line during acknowledge cycles i.e. at the ninth clock after receiving 1 byte of data. When next-to-last byte is receiving into I2CDR the I2CCR[TXAK] was zero, so this byte was acknowledged. Notice reading I2CDR allows the I2C module to receive the next byte of data on the I2C bus. Due to that we first set I2CCR[TXAK] and then read the next-to-last byte from the I2CDR. So we allow to receive the last byte but it will not acknowledged because we has set TXAK=1 already.

[martin_tcs]

Hi,

How can I detect that I am reading the next-to-last byte? Is this reported in I2CSR. I can`t find anything on this. It the STOP condition reported in some ways?
Since  the length of the data received from the master device that I am using  is never the same (1 to 8 bytes), I need to know how many bytes are sent per transaction in order to split the transaction in  a proper manner.
Thanks