New batch of T2080QDS failing on boot bank selection

[s3v]

We have a number of older T2080QDS boards that work fine.

The default flashed uboot lives in bank0 and bank4 and will print which bank it is booting from:

"boot from vBank4"
or
"boot from vBank0"

The bank can either be selected via switch positions on SW6 or by the command "qixis_reset altbank" from within uboot to select bank4 and reboot.

We're attempting to set up a new batch of purchased boards in an identical manner.

The new boards appear to, almost without fail, ignore both the dipswitch positions and the altbank command and always boot from bank0. After several hours of experimentation I was only able to get the board to boot bank4 uboot via the altbank command once. After that, I wasn't able to repeat the bank4 boot and it's been stuck at boot0 ever since.

This seems to indicate that my approach is correct, but something is acting flaky. 

My suspicion is that something is wrong with the QIXIS FPGA as it seems to be the one that drives the bank selector lines.
The FPGA version has changed between the two batches:
Old (working) prints this in uboot: FPGA: v19 (T1040QDS_2015_1208_1534)

New (not working) print this: FPGA: v22 (UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU)

Additional clue: With the dipswitches for bank selection at 000, the board boots bank0 (correct behavior).

Power off, dipswitch change (to any other bank), power on, will boot bank0 (incorrect behavior).

Power off. Power on. Board fails to boot.

It's almost as though the bank selector lines are retaining their previous settings through one power cycle.

This is not an isolated case, identical behavior is showing up in two boards of this batch so far, while older boards being flashed with the same procedure act as expected.

Any thoughts? What changes were made to the qixis fpga between version 19 and version 22 that might cause this behavior?

[garymilliorn]

Sure, I can do that if you want.  You'll need a Microsemi FlashPro3 or later.

The FPGA does not impact memory though so I don't think it will help.  D_INIT is usually a failure to see data via MDQS lines, which is typically caused by sockets not making a good connection, or sometimes mechanical issues with the DDR slots.  I would recommend reseating the T2080 first.

[leizhihualqytvw]

Dear Garymilliorn,

OK,I have FlashPro4 in hand,Would you help send the T2080QDS FPAG v23 update file to me?

However I will double check the CPU and Memeory Socket,thanks!

lzh

[garymilliorn]

Here is V21, V23 is not likely to be available for some time due to FPGA tool issues with this older code.  V21 does not have the register write-protect issue V22 introduced.

[leizhihualqytvw]

Dear GaryMilliorn,

Got it,and try it to program,but FlashPro show Fail(Failed to authenticate the encrypted data.) as below,

Are there encryption AES key or special settings in the programming software? thanks!

LZH

==================================================================

FlashPro
Version: 11.8.0.26
Release: v11.8

Software Version: 11.8.0.26
creating folder: C:\Microsemi\T2080QDS-118
Driver : 3.0.0 build 1
programmer '07824' : FlashPro4
Created new project 'C:\Microsemi\T2080QDS-118\T2080QDS-118.pro'
STAPL file 'C:\Users\bill\Desktop\T2080QDS-PA debug\T1040QDS_2019_1107_1014_V21\T1040QDS_2019_1107_1014_V21.stp' has been loaded successfully.
DESIGN : T1040QDS; CHECKSUM : E0D0; ALG_VERSION : 20
Selecting device M1A3PE1500 for debug.
programmer '07824' : Scan Chain...
programmer '07824' : Scan Chain PASSED.
programmer '07824' : Executing action PROGRAM
programmer '07824' : EXPORT FSN[48] = 912c733c445c
programmer '07824' : Data Authentication
programmer '07824' : Failed to authenticate the encrypted data.
programmer '07824' : EXPORT ERROR_CODE[16] = 8068
programmer '07824' : Finished: Fri Sep 16 10:03:03 2022 (Elapsed time 00:00:00)
Error: programmer '07824' : Executing action PROGRAM FAILED, EXIT -18, refer to FlashPro online help for details.

============================================================================

[garymilliorn]

Hmm, no we do not use encryption, these are open.

In the FlashPro SW, after "Configure Device" there's a "Procedures" button.  You can disable

"DO_ENC_AUTHENTICATION", I leave that off since it adds ~1m to programming.

[leizhihualqytvw]

Hi GaryMilliorn,

Update to V21 Ok,and I replaced the new T2080 CPU and DDR Moduler,but the issue same as before,and used the Flash Programmer(Superpro6100) to burn various versions orignal image (from QorIQ SDK2.0/SDK1.9/SDK1.8/SDK1.7) to NorFlash,Anyway can't pass the memory INIT,

When i insert different memory slot,Uboot will show different info as below, At the sametime I observe the changes of D1_MCK*, I found that when the memory is in DIMM #1, the voltage of D1_MCK* is only 20-80mV,

but when the memory is inserted into the DIMM #2 socket, D1_MCK* has a normal 933Mhz clock output and the voltage range is about 0.7V

Insert the Memory to the Slot DUT Close  "DDR3 DIMM #2"

==================================================

U-Boot 2016.012.0+ga9b437f (May 15 2016 - 18:12:07 +0800)

CPU0: T2080, Version: 1.1, (0x85300011)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1800 MHz, CPU1:1800 MHz, CPU2:1800 MHz, CPU3:1800 MHz,
CCB:600 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:150 MHz
FMAN1: 700 MHz
QMAN: 300 MHz
PME: 600 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 0c070012 0e000000 00000000 00000000
00000010: 66150002 00000000 ec027000 c1000000
00000020: 00000000 00000000 00000000 000307fc
00000030: 00000000 00000000 00000000 00000004
I2C: ready
Board: T2080QDS, Sys ID: 0x28, Board Arch: V1, Board Version: A, boot from vBank0
FPGA: v21 (T1040QDS_2019_1107_1014), build 464 on Thu Nov 07 16:14:15 2019
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=100.00MHz
SD2_CLK1=100.00MHz, SD2_CLK2=100.00MHz
SPI: ready
DRAM: Initializing....using SPD
DDR: failed to read SPD from address 81
Detected UDIMM 9JSF25672AZ-2G1K1
2 GiB (DDR3, 64-bit, CL=13, ECC on)

================================================================

Insert the Memory to the Slot DUT far  "DDR3 DIMM #1"

=================================================================

U-Boot 2016.012.0+ga9b437f (May 15 2016 - 18:12:07 +0800)

CPU0: T2080, Version: 1.1, (0x85300011)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1800 MHz, CPU1:1800 MHz, CPU2:1800 MHz, CPU3:1800 MHz,
CCB:600 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:150 MHz
FMAN1: 700 MHz
QMAN: 300 MHz
PME: 600 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 0c070012 0e000000 00000000 00000000
00000010: 66150002 00000000 ec027000 c1000000
00000020: 00000000 00000000 00000000 000307fc
00000030: 00000000 00000000 00000000 00000004
I2C: ready
Board: T2080QDS, Sys ID: 0x28, Board Arch: V1, Board Version: A, boot from vBank0
FPGA: v21 (T1040QDS_2019_1107_1014), build 464 on Thu Nov 07 16:14:15 2019
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=100.00MHz
SD2_CLK1=100.00MHz, SD2_CLK2=100.00MHz
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM 9JSF25672AZ-2G1K1
Waiting for D_INIT timeout. Memory may not work.

=================================================================

[garymilliorn]

Sorry it didn't help.  I've found D_INIT is almost always a problem with the DDR bus training failing to get MDQS reliably.  I've usually either reseated the CPU in the socket, or looked for cracks at the DIMMs (pad issues due to insertion force).

[leizhihualqytvw]

Dear Garymilliorn,

thanks for your suggestion,however i will check the ddr timing with oscilloscope,and another question about DCM/OCM sheel,i change the SW11.[7:8] DCM Control to 11 for Interactive Mode,but the UART2 havn't any OCM shell messege,How to get the OCM shell in T2080QDS? I'm not sure if I'm doing it right, Would you give me some advices?

LZH

[garymilliorn]

The mode is sampled on AC power-up (not DUT power-up).  You can restart with the EVT switch (middle of 3 pushbuttons). 

Don't expect much of it, it is primitive and only there to assist other SW with data collection.

[garymilliorn]

I know this is a while back but FYI:

V19->V22 changes involved using HRESET for DDR reset and an issue where the BRD_ID/PCBVER pins are mis-sampled, possibly resulting in the wrong target system assumed.

Printing "UUUU..." for tag info was usually due to a uboot bug that set the IFC CS2 GPCM modes incorrectly, a field was left at zero as I recall.  Was the uboot the latest?

V22 has a fairly serious bug that affects T2080 but not T1040, somehow despite being the same image.  I can fwd. V23 to you if you wish.

[leizhihualqytvw]

Dear Garymilliorn,

Would you help share Qixis FPGA V23 update file for T2080QDS to me?

 My T2080QDS board have DDR issue as below U-boot infor,however

the board's Qixis FPGA version is v7, It's very old version,I hope to update to V23, thanks!

LZH

=======================================================

U-Boot 2016.012.0+ga9b437f (May 15 2016 - 18:12:07 +0800)

CPU0: T2080, Version: 1.1, (0x85300011)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1800 MHz, CPU1:1800 MHz, CPU2:1800 MHz, CPU3:1800 MHz,
CCB:600 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:150 MHz
FMAN1: 700 MHz
QMAN: 300 MHz
PME: 600 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 0c070012 0e000000 00000000 00000000
00000010: 66150002 00000000 ec027000 c1000000
00000020: 00000000 00000000 00000000 000307fc
00000030: 00000000 00000000 00000000 00000004
I2C: ready
Board: T2080QDS, Sys ID: 0x28, Board Arch: V1, Board Version: A, boot from vBank0
FPGA: v7 (T1040QDS_2013_1120_1155), build 243 on Wed Nov 20 17:55:56 2013
SERDES Reference Clocks:
SD1_CLK1=156.25MHZ, SD1_CLK2=100.00MHz
SD2_CLK1=100.00MHz, SD2_CLK2=100.00MHz
SPI: ready
DRAM: Initializing....using SPD
Detected UDIMM 9JSF25672AZ-2G1K1
Waiting for D_INIT timeout. Memory may not work.

====================================================================

[mrbe]

Hi,

We have exactly the same problem with our T2080QDS.

this is what we can see in the console after powering on the equipment

Board: T2080QDS, Sys ID: 0x28, Board Arch: V1, Board Version: A, boot from vBank0
FPGA: v22 (UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU), build 21845 on Fri May 15 02:09:25 2015

If the solution is to upload/download the FGPA FW we need help to do so, is there any procedure or manual or guide to be sent to us in order to do so? Or should we send the equipment to the NXP facilities to do so for us? 

Thanks 

[garymilliorn]

The programming file located near the top of this page is the updated image.  To use it, you would need a Microsemi (now Microchip) FlashPro3 programmer and their Libero SW suite. The programmer is cheap but not free, the suite is huge but free.

If possible to return, I or someone could update it.  I'm not familiar with such procedures, though.