Needs further information regarding A-004447

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Needs further information regarding A-004447

Contributor I

Im'a facing an I2C issue wich seems to be related to I2C initialisation. Let me first describe my issue : I2C is going down, due to a RX NACK. I have to say that this issue regularly appears, but is not does not reproduce systematically.

When RX NACK is detected by firmware, I have no way to recover good I2C transaction. I need to shutdown my hardware. Then it goes fine.

I tried several value for SCL frequency in I2C controller register. Configuration seems to be correct.

Now, I tried to implement addendum A-004447 described for P1010 :

Nine SCL pulses cannot be generated when SDA is held low with the
sequence provided in documentation

Now, I don't see RX NACK anymore, but some transcations doesn't succed due to timeout. This timeout comes from a wait for the bus to be ready before any write or read cycle.

First, I would like to know if addendum A-004447 comes from RX NACK ?

How this should be implemtend ? In I2C init, or in write/read cycle of I2C bus ?

Do you have an explanation of value used in this implementation for register (0x00, 0x22, 0xa2 and so on) ?

Why this addendum is not implemented by OS provider (Linux for example ?)

Thanks for your help

Fabrice DECROP

This link describes the overall addendum :

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2 Replies

Contributor I fact, I'm not working under interrupt routine. I'm polling I2C slave devices, and for some unknown reasons, I get RX NACK (bit 7 of CDR is set) during the first write cycle wich is the adress of the I2C slave device.

Now, with A-004447, I dont' have anymore RX NACK (bit 7 of CDR is correctly unsetted during every write cycle), but sometimes, MIF status bit (bit 6  of CDR) is not set.

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NXP TechSupport
NXP TechSupport

It looks like that your problem concerning to RXAK bit of the P1010 I2C. There is no RX NSL bit in the P1010 I2C controller.

Setting RXAK bit is usual behavior on the I2C bus. The I2C STOP condition is needed if RXAK is set. See the Figure 10-3 of the P1010 Reference Manual Rev 4.

The A-004447 is needed for generation of SCL when SDA low. See the Section 10.6.6 of the P1010 Reference Manual.

If I2C slave hold SDA low, I2C bus is hanging.

Usually a timer is used for detection of this state.

Have a great day,
Pavel Chubakov

Note: If this post answers your question, please click the Correct Answer button. Thank you!

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