Hi Team,
We are using T2080RDB board. As per the manual for NAND boot, the SW3[4] should be one for selecting NAND and SW3[4] should be zero for selecting NOR.
Based on the Documents this pin is BOOT_SEL pin wrt to FLASH_SRC register and controlled by CPLD.
We are planning to remove CPLD in our custom board, so can we boot from NAND without using CPLD and sw3[4] which is used for boot media selection either by Hardware or software.
Can you please provide us valuable inputs to this query.
Thanks for your support.
Regards,
Irfan
