Have a great day,
You can use 78.6432MHz an external clock of 78.6432MHz for MPC860TZQ80D4 if implements reset configuration for external bus division factor bits (D[13-14]) as it is shown in section “MPC860 Reset Configuration” of the MPC860 manual.
The maximum frequency at which the SPLL is guaranteed to operate is the maximum rated frequency of the part (80MHz for MPC860TZQ80D4). Hence the SPLL can accept 78.6432MHz clock applied to EXTCLK (MODCK [1–2]=10, MF=1). However the maximum bus speed supported by the MPC860 is 66 MHz. Higher-speed part like MPC860TZQ80D must be operated in half-speed bus mode. I.e. SCCR[EBDF] has to be set to 0b01 (half speed bus) if clock generated by SPLL is higher than 66MHz. If the RSTCONF signal is negated the internal default value is selected and SCCR[EBDF] is cleared by HRESET i.e. the device starts at full speed bus. In this case the hardware specifications for the bus interface will be violated at start while applied clock of 78.6432MHz. So you need to implement reset configuration in order to set SCCR[EBDF]. Or you can divide 78.6432MHz by 2 and then after reset set 1:2:1 mode as described in the section “CLKOUT Special Considerations: 1:2:1 Mode” in the manual.
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
