MPC8377 link to samsung nand flash with CS[4], but flash ID been read is 0xFFFFFFFF

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MPC8377 link to samsung nand flash with CS[4], but flash ID been read is 0xFFFFFFFF

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jinfengzhuang
Contributor I

I have the evlution board to test my driver, it works ok, and read flash ID correctly. Now, i got another board, the nand flash has been linked to CS[4], not the origin CS[0], and all other signals are

same. I just want to read flash ID first, as it it simplest, we I scan all the banks while reading the flash ID, only the second one is not 0x0, it's 0xffffffff.

Does it means the access to nand flash is success? but why 0xffffffff ?

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r8070z
NXP TechSupport
NXP TechSupport


Have a great day,

I suppose that your driver configures all eLBC registers required by access to the NAND chip. In this case only the option and base registers should be changed for new CS pin used for the same NAND device. When NAND chip is connected to the CS[0] then the option register 0 (OR0), base register 0 (BR0) and FCM registers must be set properly for NAND control. When NAND chip is connected to the CS[4] then driver has to set the option register 4 (OR4) and Base register 4 (BR4) instead of OR0 and BR0 to the same values (i.e. values which has been set in the OR0 and BR0 for NAND connected to the CS[0]). Other operation with FCM registers are the same if the NAND device is the same.

Notice that the reference manual available on the NXP site

http://cache.nxp.com/files/32bit/doc/ref_manual/MPC8379ERM.pdf

contains section 10.5.4.2 “NAND Flash Read Status Command Sequence Example”.

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310 Views
r8070z
NXP TechSupport
NXP TechSupport


Have a great day,

I suppose that your driver configures all eLBC registers required by access to the NAND chip. In this case only the option and base registers should be changed for new CS pin used for the same NAND device. When NAND chip is connected to the CS[0] then the option register 0 (OR0), base register 0 (BR0) and FCM registers must be set properly for NAND control. When NAND chip is connected to the CS[4] then driver has to set the option register 4 (OR4) and Base register 4 (BR4) instead of OR0 and BR0 to the same values (i.e. values which has been set in the OR0 and BR0 for NAND connected to the CS[0]). Other operation with FCM registers are the same if the NAND device is the same.

Notice that the reference manual available on the NXP site

http://cache.nxp.com/files/32bit/doc/ref_manual/MPC8379ERM.pdf

contains section 10.5.4.2 “NAND Flash Read Status Command Sequence Example”.

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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309 Views
jinfengzhuang
Contributor I

thanks, after follow your word, i have also found the section:

10.5.4.3 NAND Flash Read Identification Command Sequence Example

thank you !

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