MPC8358E interface to DDR chipset

[venkat1]

Hello All,

       The following clarifications are required in interfacing MPC8358, Power QUICC II Pro Processor to a 256Mbit DDR memory device through the Primary DDR controller block of MPC8358

1.      Does End-ianness matters in connecting the DAT bus MDQ[0:31] to the DDR Device…

      Ref: MPC8360E reference Manual (MPC5360ERM Rev 3 05/2010)

       Page: Chapter 9, Page 43…9-43…Fig 9.34

       In the above Fig, its shown that, MDQ0 is conn to DQ[7] of the RAM & MDQ7 is conn to DQ[0] & so on……

       Whether this type of swapping is required as we do in the Local Bus section

2.       Is it mandatory to use error correction (ECC), as there is an option to enable or disable ERROR correction
3.        Is there a ref sch where MPC8358 DDR controller is directly interfaced to a DDR chipset & not to a        SODIMM module                                                                                                                                         Regards,
4.        Venkat                                                                                                                                                        8495952871or 98862 01027

[r8070z]

1 DDR byte lanes can be swapped and in each byte lane bits can be swapped too.

2 It is not mandatory to use error correction (ECC). It can be enabled or disabled by DDR_SDRAM_CFG[ECC_EN].

3 There was MPC8360 - SOM where MPC8360 DDR controller was directly interfaced to four 16-bit DDR chips. 

[venkat1]

Thank you sir..

 can you plz send mpc8360 SOM schematic, where 16-bit DDR chip is directly interfaced with mpc8360.
 

regards,

venkat.

[r8070z]

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