MPC8349E PCI Disable

[youngho_cho]

Hello, NXP engineers and all members of the community group.

I am working on a new board development using the MPC8394E processor.
Various other configurations were designed by getting a reference through the EVM board, etc.
However, I have a question, so I leave a message.

Our system is not a PC environment, but an embedded system environment, and all peripherals are controlled through specific controllers or local bus controller.
Therefore, I am not going to use the PCI port, and I did open or pull-up/pull-down processing according to the guide.

Assuming that the system is in PCI Host mode, I connected the PCI_SYNC_OUT pin to PCI_SYNC_IN, and then input the 66.67MHZ clock to the CLKIN pin.
Also, other reset configuration word settings were set assuming PCI Host mode.
What else do I need to set up?

Also, I did not allocate PCI memory separately on the memory map, so there will be no problems with the system operation, right?

[r8070z]

There are several hard-coded default options, selected by the reset configuration input signals, CFG_RESET_SOURCE[0:2]. Hard-coded reset configuration words are driven internally and and do not appear on any MPC834x interface. All hard-coded configuration words set

PCIHOST=0 PCI agent mode

PCI1ARB=0 External arbiter is used.

COREDIS=1 e300c1 core is disabled (boot holdoff)

BOOTSEQ=00 Boot sequencer is disabled

More details you can find in the section 4.4.3.3 Default Reset Configuration Words of the MPC8349 reference manual

These setting can be unsolvable problem for your system if there is no external PCI host which can enable the core.

Typically RCW value from CPLD or FPGA during POR loaded using the local bus. Hoever if your FPGA has PCI host port then it can configure the MPC8349 PCI agent.

>Before the device core wakes up, is it possible to access the local bus and read the values written to the FPGA?

Yes it is possible.

[r8070z]

There are several hard-coded default options, selected by the reset configuration input signals, CFG_RESET_SOURCE[0:2]. Hard-coded reset configuration words are driven internally and and do not appear on any MPC834x interface. All hard-coded configuration words set

PCIHOST=0 PCI agent mode

PCI1ARB=0 External arbiter is used.

COREDIS=1 e300c1 core is disabled (boot holdoff)

BOOTSEQ=00 Boot sequencer is disabled

More details you can find in the section 4.4.3.3 Default Reset Configuration Words of the MPC8349 reference manual

These setting can be unsolvable problem for your system if there is no external PCI host which can enable the core.

Typically RCW value from CPLD or FPGA during POR loaded using the local bus. Hoever if your FPGA has PCI host port then it can configure the MPC8349 PCI agent.

>Before the device core wakes up, is it possible to access the local bus and read the values written to the FPGA?

Yes it is possible.

[r8070z · Accepted solution]

Besides PCI host mode enable internal PCI arbiter (RCWHR[PCI1ARB] = 1). When no devices are requesting the bus, the bus is granted, or parked, for a specified device to prevent the AD, PCI_C/BE and PAR signals from floating. So after reset AD[], PCI_C/BE and PAR can be left open while it parked to the host. Correspondingly all PCI_REQx pins must be kept inactive, i.e. require for 2k-10k to power line. PCI_IDSEL tie to GND using 1k - 4.7k. Next all PCI bus control signal must be kept inactive state too. Typically it means 2k - 10k pull-up. By other words follow to “not used” column of table  PCI Bus Interface Pin Listing in the design checklist

https://www.nxp.com/docs/en/application-note/AN2931.pdf

[youngho_cho]

I appreciate your kind explanation.

I have completed the pin setting according to the contents of AN2931 that you informed me of.

I have additional questions.

According to the document AN2931,
If RCW is stored in a flash on the local bus like our system, there is an issue that the CPU core does not work because during the PORESET process, the device cannot read the RCW value before the valid RCW value is written to the flash.

In this case, there are 3 options.

Among them, first of all, if the RCW value is read with the hard-coded option, is this value saved in the boot loader?

Also, in the case of the hard-coded option, the device is shown to operate in PCI agent mode.

As in the previous inquiry, all peripherals are controlled through specific controllers or local bus controller and our system will not use the PCI bus at all.

Wouldn't it be a problem to the system operation even if booted in PCI agent mode?

Secondly, as designed as BCSR in the MPC8349EAMDSPB, if RCW value is provided as logic through CPLD or FPGA during POR, is this value input through the local bus?
Before the device core wakes up, is it possible to access the local bus and read the values written to the FPGA?

Please answer about my question.