MPC8270 SDRAM Interfacing at 100Mhz signal integrity issues

[toltol]

I am interfacing SDRAM IS45S32160F-7BLA2 with MPC8270 PowerPC Processor.

Input capacitance of SDRAM is 6pF per data line and i am using 4 SDRAM's which add upto 24pF of capacitance load.

Processor suggest to have a minimum loading of 20pF. 

Now the problem is current . Processor datasheet says Ioh = -2mA and Iol = 6mA. at Voh = 2.4 and Vol = 0.4

Keeping this current in mind, i=C dV/dT fails, as 20pF of load capacitance needs around 60mA and Iol and Ioh is 2 to 6mA , which i cannot understand?

 

Secondly when i simulated both using IBIS models, the waveform is very wierd on 4 SDRAM, So will this waveform okay for SDRAM to work on 100Mhz or i need to do something else?

Orange is input clock to SDRAM, and Red is the signal of DATA bus with 4 SDRAM's are loaded.

[alexander_yakov]

Ioh is the value of current, at which minimum voltage of Voh is guarantied, but not maximum output current.

Maximum output current is not specified in device datasheet and should be determined from IBIS model.

Signal shape on the waveform seem to be acceptable.

Please become familiar with this application note:

Interfacing SDRAM Devices to the PowerQUICC™ MPC8280 at 100 MHz

https://www.nxp.com/docs/en/application-note/AN2654.pdf 

Have a great day,
Alexander
TIC

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