¿It is possible to reinitialize the DDR controller on the MPC8548 just after his initialization? ¿How could i do that?

[diegomartin]

This is what a want to do:

1) Initialize DDR controller with no ECC and no init memory..

lis r7, 0x43000008@ha
ori r7, r7, 0x43000008@l
stw r7, DDR_SDRAM_CFG(r6)

lis r7, 0x04400000@ha
ori r7, r7, 0x04400000@l
stw r7, DDR_SDRAM_CFG_2(r6)

lis r7, 0xC3000008@ha
ori r7, r7, 0xC3000008@l
stw r7, DDR_SDRAM_CFG(r6)

2) Just After the initializacion, i want to check ram and reinitialize de DDR controler witch ECC and memory initialization. I'm trying this for the reinitialization:

lis r7, 0xC300000A@ha
ori r7, r7, 0xC300000A@l
stw r7, DDR_SDRAM_CFG(r6)

lis r7, 0x4300000A@ha
ori r7, r7, 0x4300000A@l
stw r7, DDR_SDRAM_CFG(r6)

lis r7, 0x6300000A@ha
ori r7, r7, 0x6300000A@l
stw r7, DDR_SDRAM_CFG(r6)

lis r7, 0x04400010@ha
ori r7, r7, 0x04400010@l
stw r7, DDR_SDRAM_CFG_2(r6)

lis r7, 0xE300000A@ha
ori r7, r7, 0xE300000A@l
stw r7, DDR_SDRAM_CFG(r6)

lis r7, 0xE3000008@ha
ori r7, r7, 0xE3000008@l
stw r7, DDR_SDRAM_CFG(r6)

Sometimes it works fine and other times it hangs saying that the memory is nos available.

Thank you in advance.

[r8070z]

From the DDR3 initialization flow we see that MEM_EN bit starts DDR3 device full initialization which supposed that  DDR3 device has been reset. I think your experiment confirms that. Re-initialization should starts from the DDR3 Reset.