Memory controller acts as "target" on internal bus (60x bus), responding to bus transactions from bus masters and generating internal "transfer acknowlege" bus signal to bus master, when the data is ready to be sampled by bus master. This transfer acknowledge is generated internally by GPCM controller and shown as PSDVAL signal on GPCM figures. The data is sampled by bus master, then this PSDVAL is asserted.
CS and OE control signals are outputs, generated by GPCM controller. CS timing is configurable, please look MPC8272 Reference Manual, Table 11-28 for details. For OE timing please look Section 11.5.1.4
Have a great day,
Alexander
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