Is MPC8247's data valid based on oe or cs, when it's in GPCM mode?

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Is MPC8247's data valid based on oe or cs, when it's in GPCM mode?

534 Views
linding
Contributor I

I'm confused about the timing of MPC8247's read. The "cs" and "oe" are not synchronous.

0 Kudos
3 Replies

401 Views
alexander_yakov
NXP Employee
NXP Employee

Memory controller acts as "target" on internal bus (60x bus), responding to bus transactions from bus masters and generating internal "transfer acknowlege" bus signal to bus master, when the data is ready to be sampled by bus master. This transfer acknowledge is generated internally by GPCM controller and shown as PSDVAL signal on GPCM figures. The data is sampled by bus master, then this PSDVAL is asserted.

CS and OE control signals are outputs, generated by GPCM controller. CS timing is configurable, please look MPC8272 Reference Manual, Table 11-28 for details. For OE timing please look Section 11.5.1.4


Have a great day,
Alexander

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos

401 Views
linding
Contributor I

Thanks for answering!

And I'm confused about, when MPC8247 is reading, how can it judge "the data is ready to be sampled".

And do you mean that, the "data valid" doesn't have strong relation with "cs" or "oe"?

0 Kudos

401 Views
alexander_yakov
NXP Employee
NXP Employee

GPCM supports two modes - "normal operation" and "external transfer termination".

In "normal" mode GPCM cycle is configured to have specified length in bus clock cycles, and internal "transfer acknowledge" is generated at the last cycle. In other words, it does not judge that the data is ready, it just generates read cycle according to cycle length specified in settings, and than terminates by asserting internal "transfer acknowledge" to the bus master. It is expected that cycle length is pre-configured to be enough for remote memory device to supply data before this last cycle with "transfer acknowledge" happens.

In "external transfer termination" mode GPCM has GTA input from memory device, assertion of this input causes GPCM cycle to terminate. This case is shown at Figure 11-52 of MPC8272 Reference Manual.

Regarding "CS" and "OE" - I meant "CS" is configurable and may be deasserted earlier (see Table 11-28), however this is for write cycles only. For read case "CS" and "OE" are negated at the end of GPCM cycle.

0 Kudos