Interfacing MPC860 with 4x16bit SRAM devices

[hvdmerwe]

I need assistance with an upgrade we are doing, going from 2 PowerQUICC II's, one as a Master and the second as a slave, to a singel PowerQuicc II Pro (MPC8360). We currently use 4 SRAM devices (IS61LV51216) for a 64bit external memory, and this is setup on the x60 local bus using the GPMC. 

I want to know what would be the best way to bring these same devices over on the MPC8360. Will it be using the LBC, if so, How can I get the 64 bit databus connected. Or is the DDR able to handle the connected to 4 SRAM devices?

Kind Regards

Henroux van der Merwe 

[hvdmerwe]

Thank you for the Reply. Would you be able to provide a drawing or diagram to show how this will be implemented using the UPM and 2 Chip selects. We currently use 2 74LVC841A Address latches. 

[r8070z]

Please see connections in section 10.5.5 Interfacing to ZBT SRAM  of the MPC8360 reference manual. Except the DP  signals it is like your SRAM.  The MPC8360 reference manual is avaialble on the nxp site.

[hvdmerwe]

Thank you for the assistance.

I have one more question. On the MPC8260 we kept RSTCONF asserted high for normal operation, but we pulled it low to Set the PowerQuicc to default configuration to allow us to program via the COP Programming. How does programming on the COP programmer work on the PQII Pro. 

[r8070z]

There is no way to connect 4 IS61LV51216 to the MPC8360 as a 64-bit memory. The MPC8360 64-bit DDR controller does not support SRAM. It implements the DDR1 interface i.e. multiplexed row/column address and so on. The LBC has GPCM like on PowerQuicc II, though I think UPM will be more suitable for this SRAM. However the LBS has 32-bit data bus and multiplexed addess/data (it requires for the external address latch). Under UPM control you can get burst access i.e. read/write full cache line per one address phase. Using 2 chip selects you can connect 4 IS61LV51216 as two 32-bit SRAM memory banks.