How to change 2G DRAM size in U-Boot for P2020 in SDK1.9

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How to change 2G DRAM size in U-Boot for P2020 in SDK1.9

1,114 Views
LRZ
Contributor I

Hello everyone, do you know how to change 2G DRAM size in U-Boot for P2020 in SDK1.9? I try to change p1_p2_rdb_pc.h, but uboot can't run, see log as below.

And a question, why frequency of CPU0 is 1250 MHz?


SPI Flash boot...
*** Warning - bad CRC, using default environment

DDR CONFIG FROM ddr.c
Configuring DDR for 800 MT/s data rate,total 2 GB
Need to wait up to 66 * 10ms
DDR timeout:30
CONFIG DDR FINISH
Second program loader running in sram...
Loading second stage boot loader ................................................................

U-Boot 2015.01+SDKv1.9+geb3d4fc (Oct 11 2022 - 15:18:31)

CPU0: P2020E, Version: 2.1, (0x80ea0021)
Core: e500, Version: 5.1, (0x80211051)
Clock Configuration:
CPU0:1250 MHz, CPU1:1000 MHz,
CCB:500 MHz,
DDR:400 MHz (800 MT/s data rate) (Asynchronous), LBC:31.250 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
I2C: ready
SPI: ready
DRAM:

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yipingwang
NXP TechSupport
NXP TechSupport

In u-boot source code include/configs/p1_p2_rdb_pc.h, please define the following.

#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G

792 Views
LRZ
Contributor I

=> tftp 0x1000000 vxWorks
Speed: 100, full duplex
Using eTSEC1 device
TFTP from server 192.168.0.67; our IP address is 192.168.0.101
Filename 'vxWorks'.
Load address: 0x1000000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
#############
882.8 KiB/s
done
Bytes transferred = 4002156 (3d116c hex)
=> go 0x1000000
## Starting application at 0x01000000 ...
**bleep**: 01000000 XER: 20000000 LR: 7FEFB2EC REGS: 7fdedc48 TRAP: 0700 DAR: 00000000
MSR: 00029200 EE: 1 PR: 0 FP: 0 ME: 1 IR/DR: 00

GPR00: 7FEFB2DC 7FDEDD38 7FDEDF14 00000001 7FDEEBE4 7FDEEBE4 FFFFFFFF 7FDEDC0C
GPR08: 00000001 01000000 00000020 7FDEDD38 7FF122B4 000088F5 7FFB0224 7FDEEBE0
GPR16: 7FF4F720 7FF4F718 7FDEEBD0 7FDEEC10 00000000 00000000 00000000 00000000
GPR24: 00000000 7FFB00E8 00000002 7FDEEBE0 01000000 00000002 7FF62274 7FDEEBE4
** Illegal Instruction **
Call backtrace:
7FEFB2DC 7FF17A9C 7FEF9F94 7FEFA744 7FEFA7F4 7FF16AC0 7FEFAF20
7FF40FE4 7FEFB274 7FEF164C
Program Check Exception
### ERROR ### Please RESET the board ###

 

 

How to solve the problem of failed guidance?

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970 Views
LRZ
Contributor I
And a question, why frequency of CPU0 is 1250 MHz?How to change CLK of LBC?
Clock Configuration:
CPU0:1250 MHz, CPU1:1000 MHz,
CCB:500 MHz,
DDR:400 MHz (800 MT/s data rate) (Asynchronous), LBC:31.250 MHz
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