How to Read LTSSM State in T2081 CPU

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How to Read LTSSM State in T2081 CPU

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Contributor II

I am trying to read the LTSSM state of the PCIe interface in my T2081 CPU using Codewarrior Tap. I believe that would be the PEX control/status register 0 or CSR0 register. I can't seem to find that register in the standard register list using the Debug tool in Codewarrior. Is it possible to read the LTSSM state using Codewarrior Tap?

 

Thanks,

Vinny

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4 Replies

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Contributor II

We were reading the wrong address. Since we are using PEX4 we needed offset 270000, so in u-boot the CRS0 address is 0xfe270f14 as mentioned above. In Linux you add an extra f so 0xffe270f14. When booted the LTSSM state is 0x11 as expected.

0xffe270f14 90000044 00FF0000 00000000 00008000

The difficulty now is trying to read that register while Link Training. It seems this is not possible using CodeWarrior Tap so we are attempting to create some code to do it and log the LTSSM register transitions.

Thanks,

Vinny

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NXP TechSupport
NXP TechSupport
It is needed to read 32-bit memory location with address 0xFE270F14 (for the PCIe4).
Refer to the CodeWarrior Development Studio for Power Architecture Processors Targeting Manual, 5.11 Viewing memory.

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183 Views
Contributor II

How can I read this location when the CPU is booting and link training? I don't have access to basic read/write commands during that time.

 

Thanks,

Vinny

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120 Views
NXP TechSupport
NXP TechSupport

The LTSSM value is meaningful after the training is completed - i.e. it has to be 0x11 in normal case and something else in problem cases.

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