How I can generate L1 D-Cache parity error in P2020? I am referring to e500 core document and it says: If L1CSR0[CEI] is set, any data line fill has errors injected as follows based on L1CSR0[CEIT]. Line fill operations to the L1 data cache can be created

[arsrivas]

I am trying to generate and understand handler for L1 D-Cache Parity error. After setting CEI in L1CSR0 I issued DCBF and then tried to load the same address. I got machine check. If a short code snippet to generate it can be given it will be good. Thanks

Arvind

[alexander_yakov]

P2020 processor is based on e500v2 core, but not on e500mc, so referring to E500MC Reference Manual is incorrect, please use E500 Core Reference Manual:

https://www.nxp.com/docs/en/reference-manual/E500CORERM.pdf

Please look Table 2-16 in this document.

Data cache error injections is enabled by L1CSR0[CPI]. Setting this L1CSR0[CPI] is not allowed without prior setting of L1CSR0[CPE], which enables Machine Check interrupt on cache parity error. So, the behavior you described is correct.

Have a great day,
Alexander
TIC

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[arsrivas]

Thanks for the reply. But when I tried doing so I am getting machine check as I described in the prblem. So you have any sample/demonstration code to do it?

[alexander_yakov]

Getting a machine check is an expected behavior, as I already mentioned.

No, we do not offer a demonstration code for this case.