Enabling Data Cache in MPC5675K

[komodo]

Hello All,

Would like to enable the data cache at startup assembly file. Can anyone guide me how to access the control registers and what are the steps I need to follow?

Thanks in advance for your time and help!

[marius_grigoras]

Hi,

Taking a look in the RM for e200 core [1] , this should be something like:

	asm ("mfspr	3,1010");	/* enable d-cache */
	asm ("ori		3, 3, 0x0001");
	asm ("mtspr	1010,3");

	asm ("mfspr	3,1013");	/* enable branch prediction in BUCSR */
	asm ("ori		3, 3, 0x0001");
	asm ("mtspr	1013,3");

	asm ("isync");
	asm ("msync");

Note that 1010 is an index for L1CSR0 core register and 1013 is an index for BUCSR core register.

Regards,

Marius

[1] http://www.freescale.com/files/32bit/doc/ref_manual/e200z760RM.pdf

[komodo]

Hi,

Thanks for the info!

In my task I have to specify a portion of SRAM for Data as DATA CACHE using MMU TLB table. I am not sure how MMU works with PPC. If any help to configure the memory as a data cacheable would be appreciated. Something like how to assign the RAM memory and command the controller that is use as Internal data cache.

Thanks.

[marius_grigoras]

Hi,

Please find below an example about how can configure cacheable a TLB entry:

	// 1GB  TLB entry  1: 0x00000000 - 0x3FFFFFFF; cacheable
	asm ("lis		5, 0x1001");
	asm ("ori		5, 5, 0x0000");
	asm ("mtspr	624, 5");

	asm ("lis		5, 0x8000");
	asm ("ori		5, 5, 0x0A00");
	asm ("mtspr	625, 5");

	asm ("lis		5, 0x0000");
	asm ("ori		5, 5, 0x0000	");
	asm ("mtspr	626, 5");

	asm ("lis		5, 0x0000");
	asm ("ori		5, 5, 0x0015");
	asm ("mtspr	627, 5");

	asm ("tlbwe");
	asm ("msync");
	asm ("isync"); For SRAM initialization you can take a look in the processor Reference Manual. Regards, Marius

[komodo]

Thank you very much! This helps me.