Hello,
We are trying to read data from QDR connected to virtex7 FPGA from T4240 processor in our custom board.
The processor and fpga are interfaced with PCIe. DMA channel in the T4240 processor is configured for the same.
Counter data is being written to QDR at the rate of 1ms. While we are trying to read the same counter data from the processor continuously,certain values are missing.
data read:(0..1...270...271..541..542...811..). All intermediate values are missing.
About 333ms of pause is observed between jumped values. Also, "pcie_rreq_tvalid" signal is being low for the counter values missed. The read request itself is not sent to fpga for the missed counter values.
DMA configuration is as shown;
*(unsigned int *)(mptr+DMA1_SATR0)=0x00040000 | (src >>32);
*(unsigned int *)(mptr+DMA1_DATR0)=0x00040000;
*(unsigned int*)(mptr+DMA1_BCR0)=size; //BCDMAREAD;
*(unsigned int *)(mptr+DMA1_SAR0)=src&0xFFFFFFFF; //0x04000000; //FPGA
*(unsigned int*)(mptr+DMA1_DAR0)=dest;
*(unsigned int *)(mptr+DMA1_MR0)=0xF<<24|0x4; //0x4; //Directmode , no single write , no CDSM_SWSM
*(unsigned int *)(mptr+DMA1_MR0)^=1<<0;
*(unsigned int *)(mptr+DMA1_MR0)|=1;
Every time, a delay of 333 ms is observed, due to which we are missing the counter data. Is this delay attributed to DMA configuration?
Any help in this regard is requested
Thanks in advance.