We are using the DMA Engine 2 controller to perform a DMA from a local resource connected to the eLBC bus to the DDR2 memory.
The local resource is a shared memory that can be accessed by an external master. Then the accesses to the local resource can be slowed down if the resource is used by an external master.
Randomly, the DMA engine 2 is reporting a transfer error in the DMA status register, when the accesses are slowed down in the eLBC. The DMA start correctly with a fast accesses to the local resources (around 800ns), all of them are ended by the LGTA signal.
Sometime after the fast accesses, the accesses begin to be slower (around 11 microsec.) due to the access from external master. These accesses are ended with the LGTA signal.
But, after two or three slow access the processor ends the access desasserting the control lines (chip select, output enable, and other output control signal) without the activation of the LGTA signal.
The following figure shows the signals of the local bus.
We see that the last access unexpectedly ended is sort than the previous long access, then we suppose that this access is not ended by a timeout in the local bus controller (The timeout is programmed to be 32 microsec.).
We look for other timeout sources in the processor that can explain the processor behavior. We found the Arbiter and Bus Monitor that controls and monitor the internal processor bus. We see that this arbiter has two timeouts that could be configured in the arbiter register. But we discard this timeout because the value is the maximum available of more than 60 milisec.
Please, could you help us with this problem? We need to know if there are other timeout source or if there are others explanation that could we check to understand why the processor has this unexpected behavior.
Thank you in advance.
Regards.
Manuel Ojea
