2T or 3T can be configured - refer to the LS1046A Reference Manual, 15.4.8 DDR SDRAM control configuration (DDR_SDRAM_CFG).
2T (T2_EN) should not be set if DDR_SDRAM_CFG[T3_EN] is set.
Note that RD_EN and T2_EN must not both be set at the same time.
3T (T3_EN) cannot be set if DDR_SDRAM_CFG[T2_EN] is also set.
3T timing may not be used with 4-beat bursts, unless DDR_SDRAM_CFG_2[OBC_CFG] is set.
Lowest supported Memory Bus Clock Frequency (DDR4) is 650 MHz - refer to the QorIQ LS1046A, LS1026A Data Sheet, Table 140. Processor, platform, and memory clocking specifications.