DDR3 address lines fanout

[admin]

Hi all!

I'm currently working with MPC8569 processor board design. And i'm tottaly stuck in one thing. How to make proper fanout for address lines in DDR3 interface?

For DDQ-lines it's possible to do pin swapping, so this part don't make any trouble for me. But for address, control and clk signals this is unacceptable. They are tottaly mixed up with eachother, so i don't understand how to realize so-called 'fly-by' architecture.

If there some kind of reference designs with DDR3 fly-by topology for Freescale processors, please share with me a link. Or if there is some guide for this, i'll be very appreciated.

Thanks in advance.

[r8070z]

Have a great day,

When the clock, control, command, and address buses have been routed in a fly-by topology, then each clock, control, command, and address pin on each DRAM is connected to a single trace. There is application note AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces on Freescale website.

This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem including fly-by topology.

In order to download it you can use search on top of any Freescale page. Or you can find link on Document tab of the MPC8569 Product summary page:

PowerQUICC III Processor with DDR2/3, eSDHC,|Freescale

The MPC8569MDS board uses SODIMM. DDR3 SODIMM layout can be example of the fly-by topolgy. Also DDR3 memory reference layouts can be found on JEDEC website. It requires registration. At last you can check internet for the layout example. See for instance

http://www.fedevel.com/welldoneblog/2011/02/ddr-ddr2-ddr3-pcb-layout-examples/

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[admin]

Thanks for your answer, Sergey!

Main problem for me was make proper fanout on processor side, because address pins location on processor side didn't match with they location on memory chip side. 

I have downloaded all of the JEDEC reference designs for DIMMs before i wrote my first post. But in this designs routed only memory chip side, wich with i don't have any problems, i uderstand main idea with fly-by topology.

I have been made fanout for address, control and clk lines on two layers, but they are so mixed up with each other. And i can't say now how this will affect board performance.

Design for MPC8569MDS board is in open access? Can i download it?

Thanks in advance. Заранее спасибо