DDR3 ECC Memory Connection

[aleksandrmaskin]

Hello!

I've already written in Technical Support, but surely I get here a sooner answer. I've just started a new MPC8569E project. By the way, I had never dealt with Freescale processors before. I chose Micron 8-bit DDR3 memory to be EEC. It found out that it has a combined data mask and termination data strobe ball. How can I connect it to the DDR controller? Is it possible at all?

Thanks.

[aleksandrmaskin]

I'd like to be sure that I'm right. If it is possible to swap entire 8-bit lanes in DDR3 memory IC working with MPC8569? Could problems with signal levelling emerge?

[Bulat]

For correct functioning if the 'write leveling' feature the user needs to connect MDQ0, MDQ8, MDQ16, MDQ24, MDQ32, MDQ40, MDQ48, MDQ56 and ECC0 signals of the MPC8569 to the least significant bits of the memory's byte lane, that is DQ0 for x8 and x16 devices or DQ8 for x16 devices. Other 7 bits of any byte lane can be swapped in any order.

Regards,

Bulat

[aleksandrmaskin]

Bulat, is it critical if don't pull-up MAPAR ERR input? And one more... I don't use at all the second DDR port and leave all its pins floated, is it ok?

[niranjanaradhya]

Hi All,

We have brought MPC8569MDS referance board from Freescale, using it as a referance board and desigend our own MPC8569 custom board.

We are using MPC8569, 1066.667 MHz and 1GB DDR3 module of part No: JM1333KLU-1G Transcend make.

The below are the On-board boot switch configuration in our Custom board:

  1) QE : 01000111  ;In order to make QE to work for 533 MHz

  2) DDR3 : 01110111  ; Setting DDR3 to work at 200MHz

  3) CLK : 10001001  ; Setting CCB to work at 533.33MHz and e500 core 1066.6MHz

  4) I/O : 01110001

  5) BOOT : 11011111  ; Boot from NOR flash and e500 to boot without waiting for configuration from external master.

  6) AUX : 11110011  ; MPC8569E acts as host processor, CCB freq is more than 333 MHz, Core clk > 1000 MHz

We have used Codewarrior 10.3.3 version to do memory test for DDR3 Module on our Custom board.

Issues we are facing:

If we do the Memory test using by-default Init file (.tcl) provided in the code warrior 10.3.3 directory we were getting below error and Initialization is getting failed and the DDR3 module is going to sleep mode and not waking up, resulting entire board under reset.

     "Failed to resume target process.

       writemem error: writemem.l 0xe0005000 0x010800fe failed."

we observed that "DDR Voltage is droping to zero" since ddr is going to sleep.

so we did following modification to below regsiters to continue memory test:

  1) D-Init bit in "DDR SDRAM Configuration 2" register is cleared

  2) "Write Leveling" and "DDR control driver register" is commented

  Doing Memory test using Code Warrior 10.3.3 following observation were made.

  1) DDR3 is working for 200 MHz but not for 333.33 MHz.

  2) Memory test is failing most of the times especially bus noise test is failing.

Questions:

  1) Could you please tell us whether we need to enable dinit bit in DDR_SDRAM_CFG_2 and write level registers or not?

  If so, what are the changes we need to do inorder to make DDR3 come out of sleep ?

  2) What is the reason for the BUS noise error and memory test failure ?

  3) Could you please tell us the changes in the Init file that we have to make in order to make the DDR3 work for 333.33 MHz.

Thanks in advance

[aleksandrmaskin]

I've got another question, not related to DDR3, but I'd like to place it here. MPC8569 has so-called Reset Configuration Pins that must be driven high or low. For example, LAD[0..15] define the status of the register cfg_gpinput[0..15]. That register contains the value describing "initial system configuration". And also DMA_DACK0, LA17, QE_PF9 pins defines Device ID used for RapidIO host. Am I still obliged to pull these pins up and down, if I have no need neither in getting initial system configuration nor in Rapid IO. I use only SerDes's Lane 3 and Lane 4 as SGMII.

[aleksandrmaskin]

hi, guys! I’ve got a new question. DDR3L memory chips have two Vttref (Vttca and Vttqe) inputs that should be fed with Vtt-voltage by means of separate traces. On the contrary, Freescale’s microcontroller has only one Vttref pin. What one of two traces should be connected to it?

[Bulat]

I would note that logical sequence is a bit different. I guess you have one VREF source on the board, this source should feed all Vttref inputs (typically using star topology). This includes MVREF of the processor, VREFDQ and VREFCA of the memory. Memory devices have independent VREFDQ and VREFCA inputs allowing to use different reference planes (GND or VDD) for signal routing. This is typically used on the DIMMs/SODIMMs, where data signals are referenced to GND plane, addrees/command/control - to VDD plane.

[aleksandrmaskin]

Hi, Bulat! Thank you for your response. Do you mean that situation? http://prntscr.com/2kzz1k To be honest, I draw both signals referenced to GND. And what is about processors MVREF? As I see, It doesn't matter how I route and decouple it? By the way, all my memory is on the board.

[Bulat]

Your scheme looks strange, and is difficult for comprehension (e.g. both VREFCA and VREFDQ go to D0-D7...). Only reasonable thing is a decoupling capacitor between VREFCA and VDD: yes, I meant this kind of VREFCA routing.

Since both REFs are referenced to GND you do not need two separate wires from VREF source to the memory, one is enough. MVREF signal of the processor must be referenced to GND, as well as all data group signals.

[aleksandrmaskin]

The scheme I uploaded is a fragment from SAMSUNG SO-DIMM scheme. I was in a hurry and didn't have a detailed look at it. OK, I see, a fly-by topology for Vref is also possible. Thank you again. I'm still confused when you are saying "signal referenced to the plane"... Does it mean that the signal trace are running over the GND/VDD plane a layer below?

[Bulat]

Yes, something like that. This is mostly applicable to data signals because they need to have a known impedance (typically 50-60 Ohm). For static signals like MVREF it is not so important, however it mean that decou[pling capacitors should be referenced to the same plane as associated signals. For processor's  MVREF, memory's VREFDQ and data signals it is GND. For address/command/control signals and memory's VREFCA it is up to the designer.

[Bulat]

No problem with combined DDR3's DM/TDQS pin, it should be connected to MPC8569's MDM[8] signal, i.e. Data Mask of the ECC byte. TDQS# signal of the SDRAM should be left floating. By default TDQS function is disabled on the SDRAM side, so the DM/TDQS pin functions as DM, and this is exactly what the MPC8569 needs for proper operations.

[niranjanaradhya]

Hi Bulat,

I am wonder there is no dedicated ddr reset ball on the MPC8569 IC, how to use the reset in this case for DDR3. and also where i can get the complete data sheet of MPC8569.

[Bulat]

We typically recommend to reset DDR3 devices with the same signal that is used to reset the MPC8569. You can also use a GPIO signal as DDR3 reset. In either case the reset signal going to DDR3 is required to be under DDR3 voltage rail, so a voltage converter like an open-drain circuit needs to be used.

[niranjanaradhya]

Thank you Bulat, where i can get complete data sheet for this part no.?

[andrei_skok]

It can be find on the  MPC8569E Product Summary Page

[aleksandrmaskin]

Thank you, Bulat!:smileygrin:

[LewisTse]

I suggest you should just disable the "termination data strobe" (TDQS) by setting the mode register. In other words the DM/TDQS will function as DM.

It seems TDQS is useful to provide a load as equivalent to using 4bit DDR. As our part does not support 4bit DDR at all, there is no point enabling the TDQS.

[aleksandrmaskin]

Thank you, Lewis!:smileyhappy:

[lunminliang]

Hi, there is a document AN3940 Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces

http://cache.freescale.com/files/32bit/doc/app_note/AN3940.pdf?fsrch=1&sr=1