Cannot enable the caches on MPC8260A

[eugenetodoruk]

Hello everybody,

I work with a specific board at the following frequencies:

MPC8260 Clock Configuration

- Bus-to-Core Mult 3x, VCO Div 2, 60x Bus Freq  33-100, Core Freq 100-300

- dfbrg 0, corecnf 0x08, busdf 3, cpmdf 1, plldf 0, pllmf 1, pcidf 3

- vco_out  133332000, scc_clk   33333000, brg_clk   33333000

- cpu_clk   99999000, cpm_clk   66666000, bus_clk   33333000

CPU:   MPC8260 (HiP4 Rev 14, Mask B.1 4K25A) at 99.999 MHz

Quote from the MPC8260AEC:

"The user should choose the input clock frequency and the multiplication factors such that the frequency of the CPU is equal to or greater than 150 MHz and the CPM ranges between 66–233 MHz."

Is it possible that my CPU's low frequency has somehow caused problems with caches?

Thanks

[alexander_yakov · Accepted solution]

Setting core PLL frequency below specified causes excessive PLL output jitter.

This jitter may be tolerated by core on internal core operations, but affects core to bus operations, because core and bus clock sources are different.

Core to bus operations depend on cache state - when cache is enabled, cache controller uses burst transactions for cache to bus operatons, so bus

throughput increases, and the probability of bus error due to big frequecy jitter increases also

[eugenetodoruk]

Thank you very much!

Can you explain the following?

U-boot is run from flash at 0xfff00100, then moved to the end of the SDRAM (0x0 - 0x04000000). Without the cache everything works. If I turn on the instruction cache u-boot executes exactly one instruction at the address of SDRAM, and then flies to 0xfff00000 and falls. Why is this happening?

[alexander_yakov]

There are several possible reasons for incorrect behavior after enabling instruction/data cache:

1. MMU error or disabled MMU. There are several memory-mapped device registers in IMMR space, this space should be configured as cache-inhibited. This can be done only in MMU settings. If you enable cache without MMU enabled, all memory space, including internal memory space, will become cacheable and this will result to erratic behavior.

If you need an example for MMU initialization, please look CodeWarrior installation folder, \Templates\PowerPC_EABI\Sources\G2_core\

2. SDRAM configuration error. Cache controller, when enabled, starts using burst transactions to access external SDRAM memory. If your SDRAM memory is not properly configured and can support only single transactions, than there will be an instruction/data corruption when fetching instructions from this SDRAM with instruction cache enabled.

To check this, please test your SDRAM memory with data cache enaled.

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Thank you in advance.