Blocked using Trace32 u-boot debugging and problem with hardware breakpoint

[vinothkumars]

Hi All,

We are debugging u-boot using trace32 on our new processor board with an T4240RDB.

We are currently blocked in our development. We are having problems with Trace32 debugger

hardware breakpoints

Here the situation:

    We understand that in order to get hardware breakpoints to work we need:

   1- A valid address with a valid instruction at IPVR

   2- DE bit enable in MSR register

   3- To avoid problems; always set breakpoints before or after code which accesses SRR0 and SRR1, and never step         through such code.

We have also verify that:

• Address Space is 1 (MSR IS and DS are both set to 1),
• Debug interrupt is enable (MSR DE is 1), and
• The effect of the TLB update is visible (rfi instruction should cause this to occur).

u-boot,

        lis     r6,MSR_IS|MSR_IS|MSR_DS|MSR_IS|MSR_DE@h

        ori     r6,r6,MSR_IS|MSR_IS|MSR_DS|MSR_IS|MSR_DE@l

        lis     r7,switch_as@h

        ori     r7,r7,switch_as@l

        mtspr   SPRN_SRR0,r7

        mtspr   SPRN_SRR1,r6

        rfi

After rfi instruction, jump to 0xEFFFF574 but, there is no data present and also all address same like that (data :??????????????)

Thank you,

VinothS

[rweiss]

Hi VinothS,

it seems some of the prerequisites you mention are for e500 cores and do not apply to e500mc/e5500/e6500 cores.

Please contact your local TRACE32 FAE for assistance. You can find the contact information here:

TRACE32® Worldwide Representation 

Best regards,

Reinhard

[vinothkumars · Accepted solution]

Hi Reinhard,

Thank for your reply and Instruction execute when change MSR to 0.

Regards, VinothS

[vinothkumars]

Hi,

Finally this one fixed by minimal u-boot binary (u-boot-spl.bin) instead of normal u-boot for sram.