Access the L2 cache as SRAM without rebuilding the u-boot

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Access the L2 cache as SRAM without rebuilding the u-boot

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Jerry_zhan
Contributor I
  1. On p2020 rdb board with default u-boot running, is it possible to configure the L2 cache as SRAM and access it only with u-boot commands, that is without rebuilding the u-boot?
  2. Is there any instruction to achive this goal --Configure and access L2 cache as SRAM with or without rebuilding the u-boot? 
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yipingwang
NXP TechSupport
NXP TechSupport

##################################################################################
# configure internal SRAM at 0x00000000

# L2CTL
# bit 0 = 0 - L2E: L2 SRAM disabled
# bit 1 = 0 - L2I: L2 invalidate
# bit 2-3 = 10 - L2SIZ: = 512K
# bit 13-15 = 010 - L2SRAM: One half is SRAM (256K)
mem [CCSR 0x20000] = 0x60020000

# L2SRBAR0
# bit 0-17 = BASE addr: 0x00000000
mem [CCSR 0x20100] = 0x00000000

# L2SRBAREA0
# bit 28-31 = EXTENTED BASE addr: 0x00000000
mem [CCSR 0x20104] = 0x00000000

# L2CTL
# bit 0 = 1 - L2E: L2 SRAM enable
mem [CCSR 0x20000] = 0xA0020000

 

u-boot command:

=> mw.l 0xffe20000 0x60020000
=> mw.l 0xffe20100 0x00000000
=> mw.l 0xffe20104 0x00000000
=> mw.l 0xffe20000 0xA0020000

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yipingwang
NXP TechSupport
NXP TechSupport

##################################################################################
# configure internal SRAM at 0x00000000

# L2CTL
# bit 0 = 0 - L2E: L2 SRAM disabled
# bit 1 = 0 - L2I: L2 invalidate
# bit 2-3 = 10 - L2SIZ: = 512K
# bit 13-15 = 010 - L2SRAM: One half is SRAM (256K)
mem [CCSR 0x20000] = 0x60020000

# L2SRBAR0
# bit 0-17 = BASE addr: 0x00000000
mem [CCSR 0x20100] = 0x00000000

# L2SRBAREA0
# bit 28-31 = EXTENTED BASE addr: 0x00000000
mem [CCSR 0x20104] = 0x00000000

# L2CTL
# bit 0 = 1 - L2E: L2 SRAM enable
mem [CCSR 0x20000] = 0xA0020000

 

u-boot command:

=> mw.l 0xffe20000 0x60020000
=> mw.l 0xffe20100 0x00000000
=> mw.l 0xffe20104 0x00000000
=> mw.l 0xffe20000 0xA0020000

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